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1/83 december 2004 m30l0r7000t0 m30l0r7000b0 128 mbit (8mb x16, multiple bank, multi-level, burst) 1.8v supply flash memory features summary supply voltage ?v dd = 1.7v to 2.0v for program, erase and read ?v ddq = 1.7v to 2.0v for i/o buffers ?v pp = 9v for fast program (12v tolerant) synchronous / asynchronous read ? synchronous burst read mode: 54mhz ? asynchronous page read mode ? random access: 85ns synchronous burst read suspend programming time ? 10s typical word program time using buffer program memory organization ? multiple bank memory array: 8 mbit banks ? parameter blocks (top or bottom location) dual operations ? program/erase in one bank while read in others ? no delay between read and write operations block locking ? all blocks locked at power-up ? any combination of blocks can be locked with zero latency ?wp for block lock-down ? absolute write protection with v pp = v ss security ? 64 bit unique device number ? 2112 bit user programmable otp cells common flash interface (cfi) 100,000 program/erase cycles per block figure 1. package electronic signature ? manufacturer code: 20h ? top device code: 88c4h. ? bottom device code: 88c5h package ? compliant with lead-free soldering processes ? lead-free versions tfbga88 (zaq) 8 x 10mm fbga
m30l0r7000t0, m30l0r7000b0 2/83 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. tfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 address inputs (a0-a22). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 data input/output (dq0-dq15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 chip enable (e ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 output enable (g ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 write enable (w ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 write protect (wp ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 reset (rp ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 latch enable (l ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 clock (k).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 wait (wait). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 v dd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 v ddq supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 v pp program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 v ss ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 v ssq ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 bus operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 bus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 bus write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 address latch.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 output disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 4. command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 read array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 read status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 read electronic signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 read cfi query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 clear status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3/83 m30l0r7000t0, m30l0r7000b0 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 buffer program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 buffer enhanced factory program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 setup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 program and verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 program/erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 program/erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 protection register program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 set configuration register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 block lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 block unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 block lock-down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 6. factory program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 7. electronic signature codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 5. protection register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. protection register locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 program/erase controller status bit (sr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 erase suspend status bit (sr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 erase status bit (sr5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 program status bit (sr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 v pp status bit (sr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 program suspend status bit (sr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 block protection status bit (sr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 bank write/multiple word program status bit (sr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 9. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 read select bit (cr15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 x-latency bits (cr13-cr11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 wait polarity bit (cr10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 data output configuration bit (cr9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 wait configuration bit (cr8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 burst type bit (cr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 valid clock edge bit (cr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 wrap burst bit (cr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 burst length bits (cr2-cr0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 10. configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 11. burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 6. x-latency and data output configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 7. wait configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
m30l0r7000t0, m30l0r7000b0 4/83 read modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 asynchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 synchronous burst read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 synchronous burst read suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 single synchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 dual operations and multiple bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 12. dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 13. dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 block locking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 reading a block?s lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 unlocked state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 lock-down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 locking operations during erase suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 14. lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 program and erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 15. program, erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 16. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 17. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 8. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 9. ac measurement load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 18. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 19. dc characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 20. dc characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 10.asynchronous random access read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 11.asynchronous page read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 21. asynchronous read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 12.synchronous burst read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 13.single synchronous read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 14.synchronous burst read suspend ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 15.clock input ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 22. synchronous read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 16.write ac waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 23. write ac characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 17.write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 24. write ac characteristics, chip enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 18.reset and power-up ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 25. reset and power-up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5/83 m30l0r7000t0, m30l0r7000b0 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 19.tfbga88 8x10mm - 8x10 ball array, 0.8mm pitch, bottom view package outline . . . . 52 table 26. tfbga88 8x10mm - 8x10 ball array, 0.8mm pitch, package mechanical data . . . . . . . 52 figure 20.tfbga88 daisy chain - package connections (top view through package) . . . . . . . . 53 figure 21.tfbga88 daisy chain - pcb connection proposal (top view through package) . . . . . 54 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 27. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 table 28. daisy chain ordering scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 appendix a.block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 29. top boot block addresses, m30l0r7000t0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 30. bottom boot block addresses, m30l0r7000b0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 appendix b.common flash interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 31. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 table 32. cfi query identification string. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 table 33. cfi query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 34. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 table 35. primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 36. protection register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 37. burst read information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 38. bank and erase block region information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 39. bank and erase block region 1 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 40. bank and erase block region 2 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 appendix c.flowcharts and pseudo codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 22.program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 23.buffer program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 24.program suspend & resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . 71 figure 25.block erase flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 26.erase suspend & resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 27.locking operations flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 28.protection register program flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . 75 figure 29.buffer enhanced factory program flowchart and pseudo code . . . . . . . . . . . . . . . . . . 76 appendix d.command interface state tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 41. command interface states - modify table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 42. command interface states - modify table, next output state . . . . . . . . . . . . . . . . . . . . 79 table 43. command interface states - lock table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 44. command interface states - lock table, next output state. . . . . . . . . . . . . . . . . . . . . . 81 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 45. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
m30l0r7000t0, m30l0r7000b0 6/83 summary description the m30l0r7000t0/b0 is a 128 mbit (8mbit x16) non-volatile flash memory that may be erased electrically at block level and programmed in-sys- tem on a word-by-word basis using a 1.7v to 2.0v v dd supply for the circuitry and a 1.7v to 2.0v v ddq supply for the input/output pins. an optional 9v v pp power supply is provided to speed up fac- tory programming. the device features an asymmetrical block archi- tecture and is based on a multi-level cell technolo- gy. m30l0r7000t0/b0 has an array of 131 blocks, and is divided into 8 mbit banks. there are 15 banks each containing 8 main blocks of 64 kwords, and one parameter bank containing 4 pa- rameter blocks of 16 kwords and 7 main blocks of 64 kwords. the multiple bank architecture allows dual operations, while programming or erasing in one bank, read operations are possible in other banks. only one bank at a time is allowed to be in program or erase mode. it is possible to perform burst reads that cross bank boundaries. the bank architecture is summarized in table 2. , and the memory maps are shown in figure 4. the param- eter blocks are located at the top of the memory address space for the m30l0r7000t0, and at the bottom for the m30l0r7000b0. each block can be erased separately. erase can be suspended, in order to perform program in any other block, and then resumed. program can be suspended to read data in any other block and then resumed. each block can be programmed and erased over 100,000 cycles using the supply voltage v dd . there is a buffer enhanced factory programming command available to speed up pro- gramming. program and erase commands are written to the command interface of the memory. an internal program/erase controller takes care of the tim- ings necessary for program and erase operations. the end of a program or erase operation can be detected and any error conditions identified in the status register. the command set required to control the memory is consistent with jedec stan- dards. the device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. in synchronous burst read mode, data is output on each clock cycle at fre- quencies of up to 54mhz. the synchronous burst read operation can be suspended and resumed. the device features an automatic standby mode. when the bus is inactive during asynchronous read operations, the device automatically switch- es to the automatic standby mode. in this condi- tion the power consumption is reduced to the standby value and the outputs are still driven. the m30l0r7000t0/b0 features an instant, indi- vidual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. all blocks have three levels of protection. they can be locked and locked-down individually preventing any acciden- tal programming or erasure. there is an additional hardware protection against program and erase. when v pp v pplk all blocks are protected against program or erase. all blocks are locked at power- up. the device includes 17 protection registers and 2 protection register locks, one for the first protec- tion register and the other for the 16 one-time- programmable (otp) protection registers of 128 bits each. the first protection register is divided into two segments: a 64 bit segment containing a unique device number written by st, and a 64 bit segment one-time-programmable (otp) by the user. the user programmable segment can be permanently protected. figure 5. , shows the pro- tection register memory map. the memory is available in a tfbga88, 8 x 10mm, 0.8mm pitch package. in addition to the standard version, the packages are also available in lead-free version, in compli- ance with jedec std j-std-020b, the st eco- pack 7191395 specification, and the rohs (restriction of hazardous substances) directive. all packages are compliant with lead-free solder- ing processes. the memory is supplied with all the bits erased (set to ?1?).
7/83 m30l0r7000t0, m30l0r7000b0 figure 2. logic diagram table 1. signal names ai08337 23 a0-a22 w dq0-dq15 v dd m30l0r7000t0 m30l0r7000tb e v ss 16 g rp wp v ddq v pp l k wait v ssq a0-a22 address inputs dq0-dq15 data input/outputs, command inputs e chip enable g output enable w write enable rp reset wp write protect k clock l latch enable wait wait v dd supply voltage v ddq supply voltage for input/output buffers v pp optional supply voltage for fast program & erase v ss ground v ssq ground input/output supply nc not connected internally du do not use
m30l0r7000t0, m30l0r7000b0 8/83 figure 3. tfbga connections (top view through package) ai08303 a20 nc dq5 nc nc wait d a13 a11 du a18 a4 a3 c a12 a21 nc nc b du a22 k du du a5 a 8 7 6 5 4 3 2 1 a19 g f e v ss v dd v ss nc a17 nc v pp nc a2 wp l a10 a15 a1 a7 a6 rp w a8 a14 a16 a0 dq8 dq2 dq10 dq13 nc nc a9 nc v ddq dq4 nc du j v ddq nc h nc dq0 dq7 dq14 nc m l k dq3 dq12 g dq9 dq11 dq6 e nc nc v ddq nc v ss nc v ss v dd v ss v ss v ss v ss du du du dq1 dq15
9/83 m30l0r7000t0, m30l0r7000b0 table 2. bank architecture figure 4. memory map number bank size parameter blocks main blocks parameter bank 8 mbits 4 blocks of 16 kwords 7 blocks of 64 kwords bank 1 8 mbits - 8 blocks of 64 kwords bank 2 8 mbits - 8 blocks of 64 kwords bank 3 8 mbits - 8 blocks of 64 kwords ---- ---- ---- ---- bank 14 8 mbits - 8 blocks of 64 kwords bank 15 8 mbits - 8 blocks of 64 kwords ai08338 m30l0r7000t0 - top boot block address lines a22-a0 8 main blocks bank 15 m30l0r7000b0 - bottom boot block address lines a22-a0 64 kword 000000h 00ffffh 64 kword 070000h 07ffffh 64 kword 600000h 60ffffh 64 kword 670000h 67ffffh 64 kword 680000h 68ffffh 64 kword 6f0000h 6fffffh 64 kword 700000h 70ffffh 64 kword 770000h 77ffffh 64 kword 780000h 78ffffh 64 kword 7e0000h 7effffh 16 kword 7f0000h 7f3fffh 16 kword 7fc000h 7fffffh 4 parameter blocks parameter bank parameter bank 16 kword 000000h 003fffh 16 kword 00c000h 00ffffh 64 kword 010000h 01ffffh 64 kword 070000h 07ffffh 64 kword 080000h 08ffffh 64 kword 0f0000h 0fffffh 64 kword 100000h 10ffffh 64 kword 170000h 17ffffh 64 kword 180000h 18ffffh 64 kword 1f0000h 1fffffh 64 kword 780000h 78ffffh 64 kword 7f0000h 7fffffh bank 3 bank 2 bank 1 bank 15 bank 3 bank 2 bank 1 8 main blocks 8 main blocks 8 main blocks 7 main blocks 4 parameter blocks 7 main blocks 8 main blocks 8 main blocks 8 main blocks 8 main blocks
m30l0r7000t0, m30l0r7000b0 10/83 signal descriptions see figure 2., logic diagram and table 1., signal names , for a brief overview of the signals connect- ed to this device. address inputs (a0-a22). the address inputs select the cells in the memory array to access dur- ing bus read operations. during bus write opera- tions they control the commands sent to the command interface of the internal state machine. data input/output (dq0-dq15). the data i/o outputs the data stored at the selected address during a bus read operation or inputs a command or the data to be programmed during a bus write operation. chip enable (e ). the chip enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. when chip enable is at v il and reset is at v ih the device is in active mode. when chip enable is at v ih the memory is deselected, the outputs are high impedance and the power consumption is reduced to the stand-by level. output enable (g ). the output enable controls data outputs during the bus read operation of the memory. write enable (w ). the write enable controls the bus write operation of the memory?s command interface. the data and address inputs are latched on the rising edge of chip enable or write enable whichever occurs first. write protect (wp ). write protect is an input that gives an additional hardware protection for each block. when write protect is at v il , the lock- down is enabled and the protection status of the locked-down blocks cannot be changed. when write protect is at v ih , the lock-down is disabled and the locked-down blocks can be locked or un- locked. (refer to table 14., lock status ). reset (rp ). the reset input provides a hard- ware reset of the memory. when reset is at v il , the memory is in reset mode: the outputs are high impedance and the current consumption is re- duced to the reset supply current i dd2 . refer to table 19., dc characteristics - currents , for the value of i dd2. after reset all blocks are in the locked state and the configuration register is re- set. when reset is at v ih , the device is in normal operation. exiting reset mode the device enters asynchronous read mode, but a negative transi- tion of chip enable or latch enable is required to ensure valid data outputs. the reset pin can be interfaced with 3v logic with- out any additional circuitry. it can be tied to v rph (refer to table 20., dc characteristics - voltages ). latch enable (l ). latch enable latches the ad- dress bits on its rising edge. the address latch is transparent when latch enable is at v il and it is inhibited when latch enable is at v ih . latch enable can be kept low (also at board level) when the latch enable function is not required or supported. clock (k). the clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a clock edge (rising or falling, according to the configura- tion settings) when latch enable is at v il . clock is ignored during asynchronous read and in write op- erations. wait (wait). wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. this output is high imped- ance when chip enable is at v ih , output enable is at v ih , or reset is at v il . it can be configured to be active during the wait cycle or one clock cycle in advance. v dd supply voltage . v dd provides the power supply to the internal core of the memory device. it is the main power supply for all operations (read, program and erase). v ddq supply voltage. v ddq provides the power supply to the i/o pins and enables all outputs to be powered independently from v dd . v ddq can be tied to v dd or can use a separate supply. v pp program supply voltage. v pp is both a control input and a power supply pin. the two functions are selected by the voltage range ap- plied to the pin. if v pp is kept in a low voltage range (0v to v ddq ) v pp is seen as a control input. in this case a volt- age lower than v pplk gives an absolute protection against program or erase, while v pp > v pp1 en- ables these functions (see tables 19 and 20 , dc characteristics for the relevant values). v pp is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase op- erations continue. if v pp is in the range of v pph it acts as a power supply pin. in this condition v pp must be stable un- til the program/erase algorithm is completed. v ss ground. v ss ground is the reference for the core supply. it must be connected to the system ground. v ssq ground. v ssq ground is the reference for the input/output circuitry driven by v ddq . v ssq must be connected to v ss note: each device in a system should have v dd , v ddq and v pp decoupled with a 0.1f ce- ramic capacitor close to the pin (high frequen- cy, inherently low inductance capacitors
11/83 m30l0r7000t0, m30l0r7000b0 should be as close as possible to the pack- age). see figure 9., ac measurement load cir- cuit . the pcb trace widths should be sufficient to carry the required v pp program and erase currents. bus operations there are six standard bus operations that control the device. these are bus read, bus write, ad- dress latch, output disable, standby and reset. see table 3., bus operations , for a summary. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect bus write operations. bus read. bus read operations are used to out- put the contents of the memory array, the elec- tronic signature, the status register and the common flash interface. both chip enable and output enable must be at v il in order to perform a read operation. the chip enable input should be used to enable the device. output enable should be used to gate data onto the output. the data read depends on the previous command written to the memory (see command interface section). see figures 10 , 11 , 12 and 13 read ac wave- forms, and tables 21 and 22 read ac character- istics, for details of when the output becomes valid. bus write. bus write operations write com- mands to the memory or latch input data to be programmed. a bus write operation is initiated when chip enable and write enable are at v il with output enable at v ih . commands, input data and addresses are latched on the rising edge of write enable or chip enable, whichever occurs first. the addresses can also be latched prior to the write operation by toggling latch enable. in this case the latch enable should be tied to v ih during the bus write operation. see figures 16 and 17 , write ac waveforms, and tables 23 and 24 , write ac characteristics, for details of the timing requirements. address latch. address latch operations input valid addresses. both chip enable and latch en- able must be at v il during address latch opera- tions. the addresses are latched on the rising edge of latch enable. output disable. the outputs are high imped- ance when the output enable is at v ih . standby. standby disables most of the internal circuitry allowing a substantial reduction of the cur- rent consumption. the memory is in standby when chip enable and reset are at v ih . the power con- sumption is reduced to the standby level i dd4 and the outputs are set to high impedance, indepen- dently from the output enable or write enable in- puts. if chip enable switches to v ih during a program or erase operation, the device enters standby mode when finished. reset. during reset mode the memory is dese- lected and the outputs are high impedance. the memory is in reset mode when reset is at v il . the power consumption is reduced to the standby level, independently from the chip enable, output enable or write enable inputs. if reset is pulled to v ss during a program or erase, this operation is aborted and the memory content is no longer valid. table 3. bus operations note: 1. x = don't care. 2. l can be tied to v ih if the valid address has been previously latched. 3. depends on g . 4. wait signal polarity is configured using the set configuration register command. operation e g w l rp wait (4) dq15-dq0 bus read v il v il v ih v il (2) v ih data output bus write v il v ih v il v il (2) v ih data input address latch v il x v ih v il v ih data output or hi-z (3) output disable v il v ih v ih x v ih hi-z hi-z standby v ih xxx v ih hi-z hi-z reset x x x x v il hi-z hi-z
m30l0r7000t0, m30l0r7000b0 12/83 command interface all bus write operations to the memory are inter- preted by the command interface. commands consist of one or more sequential bus write oper- ations. an internal program/erase controller han- dles all timings and verifies the correct execution of the program and erase commands. the pro- gram/erase controller provides a status register whose output may be read at any time to monitor the progress or the result of the operation. the command interface is reset to read mode when power is first applied, when exiting from re- set or whenever v dd is lower than v lko . com- mand sequences must be followed exactly. any invalid combination of commands will be ignored. refer to table 4., command codes , table 5., standard commands , and table 6., factory program command , for a summary of the com- mand interface. table 4. command codes read array command the read array command returns the addressed bank to read array mode. one bus write cycle is required to issue the read array command. once a bank is in read array mode, subsequent read operations will output the data from the memory array. a read array command can be issued to any banks while programming or erasing in another bank. if the read array command is issued to a bank currently executing a program or erase operation, the bank will return to read array mode but the program or erase operation will continue, however the data output from the bank is not guaranteed until the program or erase operation has finished. the read modes of other banks are not affected. read status register command the device contains a status register that is used to monitor program or erase operations. the read status register command is used to read the contents of the status register for the ad- dressed bank. one bus write cycle is required to issue the read status register command. once a bank is in read status register mode, subsequent read opera- tions will output the contents of the status regis- ter. the status register data is latched on the falling edge of the chip enable or output enable signals. either chip enable or output enable must be tog- gled to update the status register data the read status register command can be is- sued at any time, even during program or erase operations. the read status register command will only change the read mode of the addressed bank. the read modes of other banks are not af- fected. only asynchronous read and single syn- chronous read operations should be used to read the status register. a read array command is re- quired to return the bank to read array mode. see table 9. for the description of the status reg- ister bits. read electronic signature command the read electronic signature command is used to read the manufacturer and device codes, the lock status of the addressed bank, the protection register, and the configuration register. one bus write cycle is required to issue the read electronic signature command. once a bank is in read electronic signature mode, subsequent read operations in the same bank will output the manufacturer code, the device code, the lock hex code command 01h block lock confirm 03h set configuration register confirm 10h alternative program setup 20h block erase setup 2fh block lock-down confirm 40h program setup 50h clear status register 60h block lock setup, block unlock setup, block lock down setup and set configuration register setup 70h read status register 80h buffer enhanced factory program 90h read electronic signature 98h read cfi query b0h program/erase suspend c0h protection register program d0h program/erase resume, block erase confirm, block unlock confirm or buffer program confirm e8h buffer program ffh read array
13/83 m30l0r7000t0, m30l0r7000b0 status of the addressed bank, the protection reg- ister, or the configuration register (see table 7. ). the read electronic signature command can be issued at any time, even during program or erase operations, except during protection register pro- gram operations. if a read electronic signature command is issued to a bank that is executing a program or erase op- eration the bank will go into read electronic sig- nature mode. subsequent bus read cycles will output the electronic signature data and the pro- gram/erase controller will continue to program or erase in the background. the read electronic signature command will only change the read mode of the addressed bank. the read modes of other banks are not affected. only asynchronous read and single synchronous read operations should be used to read the elec- tronic signature. a read array command is re- quired to return the bank to read array mode. read cfi query command the read cfi query command is used to read data from the common flash interface (cfi). one bus write cycle is required to issue the read cfi query command. once a bank is in read cfi query mode, subsequent bus read operations in the same bank read from the common flash inter- face. the read cfi query command can be issued at any time, even during program or erase opera- tions. if a read cfi query command is issued to a bank that is executing a program or erase operation the bank will go into read cfi query mode. subse- quent bus read cycles will output the cfi data and the program/erase controller will continue to program or erase in the background. the read cfi query command will only change the read mode of the addressed bank. the read modes of other banks are not affected. only asyn- chronous read and single synchronous read op- erations should be used to read from the cfi. a read array command is required to return the bank to read array mode. see appendix b., common flash inter- face , tables 31 , 32 , 33 , 34 , 35 , 37 , 38 , 39 and 40 for details on the information contained in the common flash interface memory area. clear status register command the clear status register command can be used to reset (set to ?0?) all error bits (sr1, 3, 4 and 5) in the status register. one bus write cycle is required to issue the clear status register command. the clear status reg- ister command does not change the read mode of the addressed bank. the error bits in the status register do not auto- matically return to ?0? when a new command is is- sued. the error bits in the status register should be cleared before attempting a new program or erase command. block erase command the block erase command is used to erase a block. it sets all the bits within the selected block to ?1?. all previous data in the block is lost. if the block is protected then the erase operation will abort, the data in the block will not be changed and the status register will output the error. two bus write cycles are required to issue the command. the first bus cycle sets up the block erase command. the second latches the block address and starts the program/erase controller. if the second bus cycle is not the block erase con- firm code, status register bits sr4 and sr5 are set and the command is aborted. once the command is issued the bank enters read status register mode and any read opera- tion within the addressed bank will output the con- tents of the status register. a read array command is required to return the bank to read array mode. during block erase operations the bank contain- ing the block being erased will only accept the read array, read status register, read electron- ic signature, read cfi query and the program/ erase suspend command, all other commands will be ignored. the block erase operation aborts if reset, rp , goes to v il . as data integrity cannot be guaran- teed when the block erase operation is aborted, the block must be erased again. refer to dual operations section for detailed infor- mation about simultaneous operations allowed in banks not being erased. typical erase times are given in table 15., program, erase times and endurance cy- cles . see appendix c. , figure 25., block erase flow- chart and pseudo code , for a suggested flowchart for using the block erase command. program command the program command is used to program a sin- gle word to the memory array. two bus write cycles are required to issue the program command. the first bus cycle sets up the program command.
m30l0r7000t0, m30l0r7000b0 14/83 the second latches the address and data to be programmed and starts the program/erase controller. once the programming has started, read opera- tions in the bank being programmed output the status register content. during a program operation, the bank containing the word being programmed will only accept the read array, read status register, read electron- ic signature, read cfi query and the program/ erase suspend command, all other commands will be ignored. a read array command is re- quired to return the bank to read array mode. refer to dual operations section for detailed infor- mation about simultaneous operations allowed in banks not being programmed. typical program times are given in table 15., program, erase times and endurance cy- cles . the program operation aborts if reset, rp , goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the word must be reprogrammed. see appendix c. , figure 22., program flow- chart and pseudo code , for the flowchart for using the program command. buffer program command the buffer program command makes use of the device?s 32-word write buffer to speed up pro- gramming. up to 32 words can be loaded into the write buffer. the buffer program command dra- matically reduces in-system programming time compared to the standard non-buffered program command. four successive steps are required to issue the buffer program command. 1. the first bus write cycle sets up the buffer program command. the setup code can be addressed to any location within the targeted block. after the first bus write cycle, read operations in the bank will output the contents of the status register. status register bit sr7 should be read to check that the buffer is available (sr7 = 1). if the buffer is not available (sr7 = 0), re-issue the buffer program command to update the status register contents. 2. the second bus write cycle sets up the number of words to be programmed. value n is written to the same block address, where n+1 is the number of words to be programmed. 3. use n+1 bus write cycles to load the address and data for each word into the write buffer. addresses must lie within the range from the start address to the start address + n. optimum performance is obtained when the start address corresponds to a 32 word boundary. if the start address is not aligned to a 32 word boundary, the total programming time is doubled 4. the final bus write cycle confirms the buffer program command and starts the program operation. all the addresses used in the buffer program op- eration must lie within the same block. invalid address combinations or failing to follow the correct sequence of bus write cycles will set an error in the status register and abort the oper- ation without affecting the data in the memory ar- ray. if the status register bits sr4 and sr5 are set to '1', the buffer program command is not accepted. clear the status register before re-issuing the command. if the block being programmed is protected an er- ror will be set in the status register and the oper- ation will abort without affecting the data in the memory array. during buffer program operations the bank being programmed will only accept the read array, read status register, read electronic signature, read cfi query and the program/erase suspend command, all other commands will be ignored. refer to dual operations section for detailed infor- mation about simultaneous operations allowed in banks not being programmed. see appendix c, figure 27, buffer program flow- chart and pseudo code, for a suggested flowchart on using the buffer program command. buffer enhanced factory program command the buffer enhanced factory program command has been specially developed to speed up pro- gramming in manufacturing environments where the programming time is critical. it is used to program one or more write buffer(s) of 32 words to a block. once the device enters buffer enhanced factory program mode, the write buffer can be reloaded any number of times as long as the address remains within the same block. only one block can be programmed at a time. the use of the buffer enhanced factory program command requires certain operating conditions: v pp must be set to v pph v dd must be within operating range ambient temperature, t a must be 25c 5c the targeted block must be unlocked the start address must be aligned with the start of a 32 word buffer boundary
15/83 m30l0r7000t0, m30l0r7000b0 the address must remain the start address throughout programming. dual operations are not supported during the buff- er enhanced factory program operation and the command cannot be suspended. the buffer enhanced factory program command consists of three phases: the setup phase, the program and verify phase, and the exit phase, please refer to table 7. factory program com- mands for detail information. refer to table 6., factory program command , and figure 29., buffer enhanced factory program flowchart and pseudo code . setup phase. the buffer enhanced factory pro- gram command requires two bus write cycles to initiate the command. the first bus write cycle sets up the buffer enhanced factory program command. the second bus write cycle confirms the command. after the confirm command is issued, read opera- tions output the contents of the status register. the read status register command must not be issued as it will be interpreted as data to program. the status register p/e.c. bit sr7 should be read to check that the p/e.c. is ready to proceed to the next phase. if an error is detected, sr4 goes high (set to ?1?) and the buffer enhanced factory program opera- tion is terminated. see status register section for details on the error. program and verify phase. the program and verify phase requires 32 cycles to program the 32 words to the write buffer. the data is stored se- quentially, starting at the first address of the write buffer, until the write buffer is full (32 words). to program less than 32 words, the remaining words should be programmed with ffffh. three successive steps are required to issue and execute the program and verify phase of the com- mand. 1. use one bus write operation to latch the start address and the first word to be programmed. the status register bank write status bit sr0 should be read to check that the p/e.c. is ready for the next word. 2. each subsequent word to be programmed is latched with a new bus write operation. the address must remain the start address as the p/e.c. increments the address location.if any address that is not in the same block as the start address is given, the program and verify phase terminates. status register bit sr0 should be read between each bus write cycle to check that the p/e.c. is ready for the next word. 3. once the write buffer is full, the data is pro- grammed sequentially to the memory array. after the program operation the device auto- matically verifies the data and reprograms if necessary. the program and verify phase can be repeated, without re-issuing the command, to program addi- tional 32 word locations as long as the address re- mains in the same block. 4. finally, after all words, or the entire block have been programmed, write one bus write operation to any address outside the block containing the start address, to terminate program and verify phase. status register bit sr0 must be checked to deter- mine whether the program operation is finished. the status register may be checked for errors at any time but it must be checked after the entire block has been programmed. exit phase. status register p/e.c. bit sr7 set to ?1? indicates that the device has exited the buffer enhanced factory program operation and re- turned to read status register mode. a full status register check should be done to ensure that the block has been successfully programmed. see the section on the status register for more details. for optimum performance the buffer enhanced factory program command should be limited to a maximum of 100 program/erase cycles per block. if this limit is exceeded the internal algorithm will continue to work properly but some degradation in performance is possible. typical program times are given in table 15. . see appendix c. , figure 29., buffer enhanced factory program flowchart and pseudo code , for a suggested flowchart on using the buffer en- hanced factory program command. program/erase suspend command the program/erase suspend command is used to pause a program or block erase operation. the command can be addressed to any bank. the program/erase resume command is re- quired to restart the suspended operation. one bus write cycle is required to issue the pro- gram/erase suspend command. once the pro- gram/erase controller has paused bits sr7, sr6 and/ or sr2 of the status register will be set to ?1?. the following commands are accepted during pro- gram/erase suspend: ? program/erase resume ? read array (data from erase-suspended block or program-suspended word is not valid) ? read status register ? read electronic signature
m30l0r7000t0, m30l0r7000b0 16/83 ? read cfi query. additionally, if the suspended operation was erase then the following commands are also accepted: ? clear status register ? program (except in erase-suspended block) ? block lock ? block lock-down ? block unlock. during an erase suspend the block being erased can be protected by issuing the block lock or block lock-down commands. when the program/ erase resume command is issued the operation will complete. it is possible to accumulate multiple suspend oper- ations. for example: suspend an erase operation, start a program operation, suspend the program operation, then read the array. if a program command is issued during a block erase suspend, the erase operation cannot be re- sumed until the program operation has completed. the program/erase suspend command does not change the read mode of the banks. if the sus- pended bank was in read status register, read electronic signature or read cfi query mode the bank remains in that mode and outputs the corre- sponding data. refer to dual operations section for detailed infor- mation about simultaneous operations allowed during program/erase suspend. during a program/erase suspend, the device can be placed in standby mode by taking chip enable to v ih . program/erase is aborted if reset, rp , goes to v il . see appendix c. , figure 24., program suspend & resume flowchart and pseudo code , and fig- ure 26., erase suspend & resume flowchart and pseudo code , for flowcharts for using the pro- gram/erase suspend command. program/erase resume command the program/erase resume command is used to restart the program or erase operation suspended by the program/erase suspend command. one bus write cycle is required to issue the command. the command can be issued to any address. the program/erase resume command does not change the read mode of the banks. if the sus- pended bank was in read status register, read electronic signature or read cfi query mode the bank remains in that mode and outputs the corre- sponding data. if a program command is issued during a block erase suspend, then the erase cannot be re- sumed until the program operation has completed. see appendix c. , figure 24., program suspend & resume flowchart and pseudo code , and fig- ure 26., erase suspend & resume flowchart and pseudo code , for flowcharts for using the pro- gram/erase resume command. protection register program command the protection register program command is used to program the user one-time-programma- ble (otp) segments of the protection register and the two protection register locks. the device features 16 otp segments of 128 bits and one otp segment of 64 bits, as shown in fig- ure 5., protection register memory map . the segments are programmed one word at a time. when shipped all bits in the segment are set to ?1?. the user can only program the bits to ?0?. two bus write cycles are required to issue the protection register program command. the first bus cycle sets up the protection register program command. the second latches the address and data to be programmed to the protection register and starts the program/erase controller. read operations to the bank being programmed output the status register content after the pro- gram operation has started. attempting to program a previously protected pro- tection register will result in a status register er- ror. the protection register program cannot be sus- pended. the two protection register locks are used to protect the otp segments from further modifica- tion. the protection of the otp segments is not re- versible. refer to figure 5., protection register memory map , and table 8., protection register locks , for details on the lock bits. see appendix c. , figure 28., protection regis- ter program flowchart and pseudo code , for a flowchart for using the protection register pro- gram command. set configuration register command the set configuration register command is used to write a new value to the configuration register. two bus write cycles are required to issue the set configuration register command. the first cycle sets up the set configuration register command and the address corresponding to the configuration register content. the second cycle writes the configuration register data and the confirm command. the configuration register data must be written as an address during the bus write cycles, that is
17/83 m30l0r7000t0, m30l0r7000b0 a0 = cr0, a1 = cr1, ?, a15 = cr15. addresses a16- a22 are ignored. once the set configuration register command has been issued, read operations will output the array contents. the read electronic signature command is re- quired to read the updated contents of the config- uration register. block lock command the block lock command is used to lock a block and prevent program or erase operations from changing the data in it. all blocks are locked after power-up or reset. two bus write cycles are required to issue the block lock command. the first bus cycle sets up the block lock command. the second bus write cycle latches the block address and locks the block. the lock status can be monitored for each block using the read electronic signature command. table 14. shows the lock status after issuing a block lock command. once set, the block lock bits remain set until a hardware reset or power-down/power-up. they are cleared by a block unlock command. refer to the section, block locking, for a detailed explanation. see appendix c. , figure 27., locking operations flowchart and pseudo code , for a flowchart for using the lock command. block unlock command the block unlock command is used to unlock a block, allowing the block to be programmed or erased. two bus write cycles are required to issue the block unlock command. the first bus cycle sets up the block unlock command. the second bus write cycle latches the block address and unlocks the block. the lock status can be monitored for each block using the read electronic signature command. table 14. shows the protection status after issuing a block unlock command. refer to the section, block locking, for a detailed explanation and appendix c. , figure 27., locking operations flowchart and pseudo code , for a flowchart for using the block unlock command. block lock-down command the block lock-down command is used to lock- down a locked or unlocked block. a locked-down block cannot be programmed or erased. the lock status of a locked-down block cannot be changed when wp is low, v il . when wp is high, v ih, the lock-down function is disabled and the locked blocks can be individually unlocked by the block unlock command. two bus write cycles are required to issue the block lock-down command. the first bus cycle sets up the block lock- down command. the second bus write cycle latches the block address and locks-down the block. the lock status can be monitored for each block using the read electronic signature command. locked-down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. table 14. shows the lock status af- ter issuing a block lock-down command. refer to the section, block locking, for a detailed explanation and appendix c. , figure 27., locking operations flowchart and pseudo code , for a flowchart for using the lock-down command.
m30l0r7000t0, m30l0r7000b0 18/83 table 5. standard commands note: 1. x = don't care, wa=word address in targeted bank, rd=read data, srd=status register data, esd=electronic signature data, qd=query data, ba=block address, bka= bank address, pd=program data, pra=protection register address, prd=protection register data, crd=configuration register data. 2. must be same bank as in the first cycle. the signature addresses are listed in table 7. 3. any address within the bank can be used. 4. n+1 is the number of words to be programmed. commands cycles bus operations 1st cycle 2nd cycle op. add data op. add data read array 1+ write bka ffh read wa rd read status register 1+ write bka 70h read bka (2) srd read electronic signature 1+ write bka 90h read bka (2) esd read cfi query 1+ write bka 98h read bka (2) qd clear status register 1 write bka 50h block erase 2 write bka or ba (3) 20h write ba d0h program 2 write bka or wa (3) 40h or 10h write wa pd buffer program n+4 write ba e8h write ba n write pa 1 pd 1 write pa 2 pd 2 write pa n+1 pd n+1 write x d0h program/erase suspend 1 write x b0h program/erase resume 1 write x d0h protection register program 2 write pra c0h write pra prd set configuration register 2 write crd 60h write crd 03h block lock 2 write bka or ba (3) 60h write ba 01h block unlock 2 write bka or ba (3) 60h write ba d0h block lock-down 2 write bka or ba (3) 60h write ba 2fh
19/83 m30l0r7000t0, m30l0r7000b0 table 6. factory program command note: 1. wa=word address in targeted bank, bka= bank addres s, pd=program data, ba=block address, x = don?t care. 2. wa 1 is the start address, not ba 1 = not block address of wa 1 . 3. the program/verify phase can be executed any number of times as long as the data is to be programmed to the same block. 4. any address within the bank can be used. table 7. electronic signature codes note: cr = configuration register, prld = protection register lock data. command phase cycles bus write operations 1st 2nd 3rd final -1 final add data add data add data add data add data buffer enhanced factory program setup 2 bka or wa (4) 80h wa 1 d0h program/ verify (3)) 32 wa 1 pd 1 wa 1 pd 2 wa 1 pd 3 wa 1 pd 31 wa 1 pd 32 exit 1 not ba 1 (2) x code address (h) data (h) manufacturer code bank address + 00 0020 device code top bank address + 01 88c4 bottom bank address + 01 88c5 block protection locked block address + 02 0001 unlocked 0000 locked and locked-down 0003 unlocked and locked-down 0002 configuration register bank address + 05 cr protection register pr0 lock st factory default bank address + 80 0002 otp area permanently locked 0000 protection register pr0 bank address + 81 bank address + 84 unique device number bank address + 85 bank address + 88 otp area protection register pr1 through pr16 lock bank address + 89 prld protection registers pr1-pr16 bank address + 8a bank address + 109 otp area
m30l0r7000t0, m30l0r7000b0 20/83 figure 5. protection register memory map ai07563 user programmable otp unique device number protection register lock 1 0 88h 88h 85h 84h 81h 80h user programmable otp protection registers user programmable otp protection register lock 10 432 975 13 12 10 11 8 6 14 15 pr1 pr16 pr0 89h 8ah 91h 102h 109h
21/83 m30l0r7000t0, m30l0r7000b0 table 8. protection register locks lock description number address bits lock 1 80h bit 0 preprogrammed to protect unique device number, address 81h to 84h in pr0 bit 1 protects 64bits of otp segment, address 85h to 88h in pr0 bits 2 to 15 reserved lock 2 89h bit 0 protects 128bits of otp segment pr1 bit 1 protects 128bits of otp segment pr2 bit 2 protects 128bits of otp segment pr3 ---- ---- bit 13 protects 128bits of otp segment pr14 bit 14 protects 128bits of otp segment pr15 bit 15 protects 128bits of otp segment pr16
m30l0r7000t0, m30l0r7000b0 22/83 status register the status register provides information on the current or previous program or erase operations. issue a read status register command to read the contents of the status register, refer to read status register command section for more de- tails. to output the contents, the status register is latched and updated on the falling edge of the chip enable or output enable signals and can be read until chip enable or output enable returns to v ih . the status register can only be read using single asynchronous or single synchronous reads. bus read operations from any address within the bank, always read the status register during program and erase operations. the various bits convey information about the sta- tus and any errors of the operation. bits sr7, sr6, sr2 and sr0 give information on the status of the device and are set and reset by the device. bits sr5, sr4, sr3 and sr1 give information on er- rors, they are set by the device but must be reset by issuing a clear status register command or a hardware reset. if an error bit is set to ?1? the status register should be reset before issuing another command. the bits in the status register are summarized in table 9., status register bits . refer to table 9. in conjunction with the following text descriptions. program/erase controller status bit (sr7). the program/erase controller status bit indicates whether the program/erase controller is active or inactive in any bank. when the program/erase controller status bit is low (set to ?0?), the program/erase controller is active; when the bit is high (set to ?1?), the pro- gram/erase controller is inactive, and the device is ready to process a new command. the program/erase controller status bit is low immediately after a program/erase suspend com- mand is issued until the program/erase controller pauses. after the program/erase controller paus- es the bit is high. erase suspend status bit (sr6). the erase suspend status bit indicates that an erase opera- tion has been suspended in the addressed block. when the erase suspend status bit is high (set to ?1?), a program/erase suspend command has been issued and the memory is waiting for a pro- gram/erase resume command. the erase suspend status bit should only be con- sidered valid when the program/erase controller status bit is high (program/erase controller inac- tive). sr6 is set within the erase suspend latency time of the program/erase suspend command be- ing issued therefore the memory may still com- plete the operation rather than entering the suspend mode. when a program/erase resume command is is- sued the erase suspend status bit returns low. erase status bit (sr5). the erase status bit is used to identify if there was an error during a block or bank erase operation. when the erase status bit is high (set to ?1?), the program/erase control- ler has applied the maximum number of pulses to the block or bank and still failed to verify that it has erased correctly. the erase status bit should be read once the pro- gram/erase controller status bit is high (program/ erase controller inactive). once set high, the erase status bit must be set low by a clear status register command or a hardware reset before a new erase command is is- sued, otherwise the new command will appear to fail. program status bit (sr4). the program status bit is used to identify if there was an error during a program operation. the program status bit should be read once the program/erase controller status bit is high (pro- gram/erase controller inactive). when the program status bit is high (set to ?1?), the program/erase controller has applied the maximum number of pulses to the word and still failed to verify that it has programmed correctly. attempting to program a '1' to an already pro- grammed bit while v pp = v pph will also set the program status bit high. if v pp is different from v pph , sr4 remains low (set to '0') and the attempt is not shown. once set high, the program status bit must be set low by a clear status register command or a hardware reset before a new program command is issued, otherwise the new command will appear to fail. v pp status bit (sr3). the v pp status bit is used to identify an invalid voltage on the v pp pin during program and erase operations. the v pp pin is only sampled at the beginning of a program or erase operation. program and erase operations are not guaranteed if v pp becomes invalid during an oper- ation. when the v pp status bit is low (set to ?0?), the volt- age on the v pp pin was sampled at a valid voltage. when the v pp status bit is high (set to ?1?), the v pp pin has a voltage that is below the v pp lockout voltage, v pplk , the memory is protected and pro- gram and erase operations cannot be performed. once set high, the v pp status bit must be set low by a clear status register command or a hard- ware reset before a new program or erase com- mand is issued, otherwise the new command will appear to fail.
23/83 m30l0r7000t0, m30l0r7000b0 program suspend status bit (sr2). the pro- gram suspend status bit indicates that a program operation has been suspended in the addressed block. the program suspend status bit should only be considered valid when the program/erase controller status bit is high (program/erase con- troller inactive). when the program suspend status bit is high (set to ?1?), a program/erase suspend command has been issued and the memory is waiting for a pro- gram/erase resume command. sr2 is set within the program suspend latency time of the program/erase suspend command be- ing issued therefore the memory may still com- plete the operation rather than entering the suspend mode. when a program/erase resume command is is- sued the program suspend status bit returns low. block protection status bit (sr1). the block protection status bit is used to identify if a pro- gram or block erase operation has tried to modify the contents of a locked block. when the block protection status bit is high (set to ?1?), a program or erase operation has been at- tempted on a locked block. once set high, the block protection status bit must be set low by a clear status register com- mand or a hardware reset before a new program or erase command is issued, otherwise the new command will appear to fail. bank write/multiple word program status bit (sr0). the bank write status bit indicates wheth- er the addressed bank is programming or erasing. in buffer enhanced factory program mode the multiple word program bit shows if the device is ready to accept a new word to be programmed to the memory array. the bank write status bit should only be consid- ered valid when the program/erase controller sta- tus sr7 is low (set to ?0?). when both the program/erase controller status bit and the bank write status bit are low (set to ?0?), the addressed bank is executing a program or erase operation. when the program/erase con- troller status bit is low (set to ?0?) and the bank write status bit is high (set to ?1?), a program or erase operation is being executed in a bank other than the one being addressed. in buffer enhanced factory program mode if mul- tiple word program status bit is low (set to ?0?), the device is ready for the next word, if the multi- ple word program status bit is high (set to ?1?) the device is not ready for the next word. for further details on how to use the status regis- ter, see the flowcharts and pseudocodes provid- ed in appendix c.
m30l0r7000t0, m30l0r7000b0 24/83 table 9. status register bits note: logic level '1' is high, '0' is low. bit name type logic level definition sr7 p/e.c. status status '1' ready '0' busy sr6 erase suspend status status '1' erase suspended '0' erase in progress or completed sr5 erase status error '1' erase error '0' erase success sr4 program status error '1' program error '0' program success sr3 v pp status error '1' v pp invalid, abort '0' v pp ok sr2 program suspend status status '1' program suspended '0' program in progress or completed sr1 block protection status error '1' program/erase on protected block, abort '0' no operation to protected blocks sr0 bank write status status '1' sr7 = ?1? not allowed sr7 = ?0? program or erase operation in a bank other than the addressed bank '0' sr7 = ?1? no program or erase operation in the device sr7 = ?0? program or erase operation in addressed bank multiple word program status (buffer enhanced factory program mode) status '1' sr7 = ?1? not allowed sr7 = ?0? the device is not ready for the next word '0' sr7 = ?1? the device is exiting from befp sr7 = ?0? the device is ready for the next word
25/83 m30l0r7000t0, m30l0r7000b0 configuration register the configuration register is used to configure the type of bus access that the memory will per- form. refer to read modes section for details on read operations. the configuration register is set through the command interface using the set configuration register command. after a reset or power-up the device is configured for asynchronous read (cr15 = 1). the configuration register bits are described in table 10. they specify the selection of the burst length, burst type, burst x latency and the read op- eration. refer to figures 6 and 7 for examples of synchronous burst configurations. read select bit (cr15) the read select bit, cr15, is used to switch be- tween asynchronous and synchronous read op- erations. when the read select bit is set to ?1?, read opera- tions are asynchronous; when the read select bit is set to ?0?, read operations are synchronous. synchronous burst read is supported in both pa- rameter and main blocks and can be performed across banks. on reset or power-up the read select bit is set to ?1? for asynchronous access (default). x-latency bits (cr13-cr11) the x-latency bits are used during synchronous read operations to set the number of clock cycles between the address being latched and the first data becoming available. for correct operation the x-latency bits can only assume the values in table 10., configuration register . the correspondence between x-latency settings and the maximum sustainable frequency must be calculated taking into account some system pa- rameters. two conditions must be satisfied: 1. depending on whether t avk_cpu or t delay is supplied either one of the following two equations must be satisfied: (n + 1) t k t avqv - t avk_cpu + t qvk_cpu (n + 2) t k t avqv + t delay + t qvk_cpu 2. and also t k > t kqv + t qvk_cpu where n is the chosen x-latency configuration code t k is the clock period t avk_cpu is clock to address valid, l low, or e low, whichever occurs last t delay is address valid, l low, or e low to clock, whichever occurs last t qvk_cpu is the data setup time required by the system cpu, t kqv is the clock to data valid time t avqv is the random access time of the device. refer to figure 6., x-latency and data output configuration example . wait polarity bit (cr10) the wait polarity bit is used to set the polarity of the wait signal used in synchronous burst read mode. during synchronous burst read mode the wait signal indicates whether the data output are valid or a wait state must be inserted. when the wait polarity bit is set to ?0? the wait sig- nal is active low. when the wait polarity bit is set to ?1? the wait signal is active high (default). data output configuration bit (cr9) the data output configuration bit is used to con- figure the output to remain valid for either one or two clock cycles during synchronous mode. when the data output configuration bit is ?0? the output data is valid for one clock cycle, when the data output configuration bit is ?1? the output data is valid for two clock cycles. the data output configuration must be config- ured using the following condition: t k > t kqv + t qvk_cpu where t k is the clock period t qvk_cpu is the data setup time required by the system cpu t kqv is the clock to data valid time. if this condition is not satisfied, the data output configuration bit should be set to ?1? (two clock cy- cles). refer to figure 6., x-latency and data out- put configuration example . wait configuration bit (cr8) the wait configuration bit is used to control the timing of the wait output pin, wait, in synchro- nous burst read mode. when wait is asserted, data is not valid and when wait is de-asserted, data is valid. when the wait configuration bit is low (set to ?0?) the wait output pin is asserted during the wait state. when the wait configuration bit is high (set to ?1?) (default) the wait output pin is asserted one clock cycle before the wait state. burst type bit (cr7) the burst type bit determines the sequence of ad- dresses read during synchronous burst reads. the burst type bit is high (set to ?1?), as the mem- ory outputs from sequential addresses only.
m30l0r7000t0, m30l0r7000b0 26/83 see table 11., burst type definition , for the se- quence of addresses output from a given starting address in sequential mode. valid clock edge bit (cr6) the valid clock edge bit, cr6, is used to config- ure the active edge of the clock, k, during syn- chronous read operations. when the valid clock edge bit is low (set to ?0?) the falling edge of the clock is the active edge. when the valid clock edge bit is high (set to ?1?) the rising edge of the clock is the active edge. wrap burst bit (cr3) the wrap burst bit, cr3, is used to select be- tween wrap and no wrap. synchronous burst reads can be confined inside the 4, 8 or 16 word boundary (wrap) or overcome the boundary (no wrap). when the wrap burst bit is low (set to ?0?) the burst read wraps. when it is high (set to ?1?) the burst read does not wrap. burst length bits (cr2-cr0) the burst length bits are used to set the number of words to be output during a synchronous burst read operation as result of a single address latch cycle. they can be set for 4 words, 8 words, 16 words or continuous burst, where all the words are read sequentially. in continuous burst mode the burst sequence can cross bank boundaries. in continuous burst mode, in 4, 8 or 16 words no- wrap, depending on the starting address, the de- vice asserts the wait signal to indicate that a de- lay is necessary before the data is output. if the starting address is aligned to a 4 word boundary no wait states are needed and the wait output is not asserted. if the starting address is shifted by 1, 2 or 3 posi- tions from the four word boundary, wait will be asserted for 1, 2 or 3 clock cycles when the burst sequence crosses the first 16 word boundary, to indicate that the device needs an internal delay to read the successive words in the array. wait will be asserted only once during a continuous burst access. see also table 11., burst type definition . cr14, cr5 and cr4 are reserved for future use.
27/83 m30l0r7000t0, m30l0r7000b0 table 10. configuration register bit description value description cr15 read select 0 synchronous read 1 asynchronous read (default at power-on) cr14 reserved cr13-cr11 x-latency 010 2 clock latency 011 3 clock latency 100 4 clock latency 101 5 clock latency 111 reserved (default) other configurations reserved cr10 wait polarity 0 wait is active low 1 wait is active high (default) cr9 data output configuration 0 data held for one clock cycle 1 data held for two clock cycles (default) cr8 wait configuration 0 wait is active during wait state 1 wait is active one data cycle before wait state (default) cr7 burst type 0 reserved 1 sequential (default) cr6 valid clock edge 0 falling clock edge 1 rising clock edge (default) cr5-cr4 reserved cr3 wrap burst 0wrap 1 no wrap (default) cr2-cr0 burst length 001 4 words 010 8 words 011 16 words 111 continuous (default)
m30l0r7000t0, m30l0r7000b0 28/83 table 11. burst type definition mode start add 4 words 8 words 16 words continuous burst sequential sequential sequential wrap 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13- 14-15 0-1-2-3-4-5-6... 1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11-12-13-14- 15-0 1-2-3-4-5-6-7-...15-wait-16- 17-18... 2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12-13-14- 15-0-1 2-3-4-5-6-7...15-wait-wait- 16-17-18... 3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13-14-15- 0-1-2 3-4-5-6-7...15-wait-wait- wait-16-17-18... ... 7 7-4-5-6 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-0-1-2-3- 4-5-6 7-8-9-10-11-12-13-14-15- wait-wait-wait-16-17... ... 12 12-13-14-15-16-17-18... 13 13-14-15-wait-16-17-18... 14 14-15-wait-wait-16-17-18.... 15 15-wait-wait-wait-16-17- 18... no-wrap 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13- 14-15 same as for wrap (wrap /no wrap has no effect on continuous burst) 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8-9-10-11-12-13-14- 15-wait-16 2 2-3-4-5 2-3-4-5-6-7-8-9... 2-3-4-5-6-7-8-9-10-11-12-13-14- 15-wait-wait-16-17 3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7-8-9-10-11-12-13-14-15- wait-wait-wait- 16-17-18 ... 7 7-8-9-10 7-8-9-10-11-12-13-14 7-8-9-10-11-12-13-14-15-wait- wait-wait-16-17-18-19-20-21-22 ... 12 12-13-14-15 12-13-14-15-16-17- 18-19 12-13-14-15-16-17-18-19-20-21- 22-23-24-25-26-27 13 13-14-15-wait- 16 13-14-15-wait-16- 17-18-19-20 13-14-15-wait-16-17-18-19-20- 21-22-23-24-25-26-27-28 14 14-15-wait- wait-16-17 14-15-wait-wait- 16-17-18-19-20-21 14-15-wait-wait-16-17-18-19- 20-21-22-23-24-25-26-27-28-29 15 15-wait-wait- wait-16-17-18 15-wait-wait- wait-16-17-18-19- 20-21-22 15-wait-wait-wait-16-17-18-19- 20-21-22-23-24-25-26-27-28-29- 30
29/83 m30l0r7000t0, m30l0r7000b0 figure 6. x-latency and data output configuration example figure 7. wait configuration example ai06182 a22-a0 valid address k l dq15-dq0 valid data x-latency valid data tacc tavk_cpu tk tqvk_cpu tqvk_cpu tkqv 1st cycle 2nd cycle 3rd cycle 4th cycle note. settings shown: x-latency = 4, data output held for one clock cycle e tdelay ai06972 a22-a0 valid address k l dq15-dq0 valid data wait cr8 = '0' cr10 = '0' wait cr8 = '1' cr10 = '0' valid data not valid valid data e wait cr8 = '0' cr10 = '1' wait cr8 = '1' cr10 = '1'
m30l0r7000t0, m30l0r7000b0 30/83 read modes read operations can be performed in two different ways depending on the settings in the configura- tion register. if the clock signal is ?don?t care? for the data output, the read operation is asynchro- nous; if the data output is synchronized with clock, the read operation is synchronous. the read mode and format of the data output are determined by the configuration register. (see configuration register section for details). all banks support both asynchronous and synchro- nous read operations. asynchronous read mode in asynchronous read operations the clock signal is ?don?t care?. the device outputs the data corre- sponding to the address latched, that is the mem- ory array, status register, common flash interface or electronic signature depending on the command issued. cr15 in the configuration reg- ister must be set to ?1? for asynchronous opera- tions. asynchronous read operations can be performed in two different ways, asynchronous random ac- cess read and asynchronous page read. only asynchronous page read takes full advantage of the internal page storage so different timings are applied. in asynchronous read mode a page of data is in- ternally read and stored in a page buffer. the page has a size of 4 words and is addressed by address inputs a0 and a1. the first read operation within the page has a longer access time (t avqv , random access time), subsequent reads within the same page have much shorter access times (t avqv1 , page access time). if the page changes then the normal, longer timings apply again. the device features an automatic standby mode. during asynchronous read operations, after a bus inactivity of 150ns, the device automatically switches to the automatic standby mode. in this condition the power consumption is reduced to the standby value and the outputs are still driven. in asynchronous read mode, the wait signal is always de-asserted. see table 21., asynchronous read ac charac- teristics , figure 10., asynchronous random ac- cess read ac waveforms , and figure 11., asynchronous page read ac waveforms , for details. synchronous burst read mode in synchronous burst read mode the data is out- put in bursts synchronized with the clock. it is pos- sible to perform burst reads across bank boundaries. synchronous burst read mode can only be used to read the memory array. for other read opera- tions, such as read status register, read cfi and read electronic signature, single synchro- nous read or asynchronous random access read must be used. in synchronous burst read mode the flow of the data output depends on parameters that are con- figured in the configuration register. a burst sequence starts at the first clock edge (ris- ing or falling depending on valid clock edge bit cr6 in the configuration register) after the falling edge of latch enable or chip enable, whichever occurs last. addresses are internally incremented and data is output on each data cycle after a delay which depends on the x latency bits cr13-cr11 of the configuration register. the number of words to be output during a syn- chronous burst read operation can be configured as 4 words, 8 words, 16 words or continuous (burst length bits cr2-cr0). the data can be configured to remain valid for one or two clock cy- cles (data output configuration bit cr9). the order of the data output can be modified through the wrap burst bit in the configuration register. the burst sequence is sequential and can be confined inside the 4, 8 or 16 word bound- ary (wrap) or overcome the boundary (no wrap). the wait signal may be asserted to indicate to the system that an output delay will occur. this de- lay will depend on the starting address of the burst sequence and on the burst configuration. wait is asserted during the x latency, the wait state and at the end of a 4, 8 and 16 word burst. it is only de-asserted when output data are valid. in continuous burst read mode a wait state will oc- cur when crossing the first 16 word boundary. if the burst starting address is aligned to a 4 word page, the wait state will not occur. the wait signal can be configured to be active low or active high by setting cr10 in the config- uration register. see table 22., synchronous read ac character- istics , and figure 12., synchronous burst read ac waveforms , for details. synchronous burst read suspend. a syn- chronous burst read operation can be suspend- ed, freeing the data bus for other higher priority devices. it can be suspended during the initial ac- cess latency time (before data is output) in which case the initial latency time can be reduced to ze- ro, or after the device has output data. when the synchronous burst read operation is suspended, internal array sensing continues and any previous- ly latched internal data is retained. a burst se-
31/83 m30l0r7000t0, m30l0r7000b0 quence can be suspended and resumed as often as required as long as the operating conditions of the device are met. a synchronous burst read operation is suspend- ed when chip enable, e , is low and the current address has been latched (on a latch enable ris- ing edge or on a valid clock edge). the clock sig- nal is then halted at v ih or at v il , and output enable, g , goes high. when output enable, g , becomes low again and the clock signal restarts, the synchronous burst read operation is resumed exactly where it stopped. wait will revert to high-impedance when output enable, g , or chip enable, e , goes high. see table 22., synchronous read ac character- istics , and figure 14., synchronous burst read suspend ac waveforms , for details. single synchronous read mode single synchronous read operations are similar to synchronous burst read operations except that the memory outputs the same data to the end of the operation. synchronous single reads are used to read the electronic signature, status register, cfi, block protection status, configuration register status or protection register. when the addressed bank is in read cfi, read status register or read electronic signature mode, the wait signal is as- serted during the x latency, the wait state and at the end of a 4, 8 and 16 word burst. it is only de- asserted when output data are valid. see table 22., synchronous read ac character- istics , and figure 12., synchronous burst read ac waveforms , for details.
m30l0r7000t0, m30l0r7000b0 32/83 dual operations and multiple bank architecture the multiple bank architecture of the m30l0r7000t0/b0 gives greater flexibility for software developers to split the code and data spaces within the memory array. the dual opera- tions feature simplifies the software management of the device by allowing code to be executed from one bank while another bank is being programmed or erased. the dual operations feature means that while pro- gramming or erasing in one bank, read operations are possible in another bank with zero latency (only one bank at a time is allowed to be in pro- gram or erase mode). if a read operation is required in a bank, which is programming or erasing, the program or erase op- eration can be suspended. also if the suspended operation was erase then a program command can be issued to another block, so the device can have one block in erase suspend mode, one programming and other banks in read mode. bus read operations are allowed in another bank between setup and confirm cycles of program or erase operations. by using a combination of these features, read op- erations are possible at any moment in the m30l0r7000t0/b0 device. tables 12 and 13 show the dual operations possi- ble in other banks and in the same bank. table 12. dual operations allowed in other banks table 13. dual operations allowed in same bank note: 1. not allowed in the block or word that is being erased or programmed. 2. the read array command is accepted but the data output is not guaranteed until the program or erase has completed. status of bank commands allowed in another bank read array read status register read cfi query read electronic signature program, buffer program block erase program/ erase suspend program/ erase resume i dle ye s ye s ye s yes ye s ye s yes yes programming yes yes yes yes ? ? yes ? erasing yes yes yes yes ? ? yes ? program suspended yes yes yes yes ? ? ? yes erase suspended yes yes yes yes yes ? ? yes status of bank commands allowed in same bank read array read status register read cfi query read electronic signature program, buffer program block erase program/ erase suspend program/ erase resume idle yes yes yes yes yes yes yes yes programming ? (2) yes yes yes ? ? yes ? erasing ? (2) yes yes yes ? ? yes ? program suspended yes (1) yes yes yes ? ? ? yes erase suspended yes (1) ye s yes yes yes (1) ?? yes
33/83 m30l0r7000t0, m30l0r7000b0 block locking the m30l0r7000t0/b0 features an instant, indi- vidual block locking scheme that allows any block to be locked or unlocked with no latency. this lock- ing scheme has three levels of protection. lock/unlock - this first level allows software only control of block locking. lock-down - this second level requires hardware interaction before locking can be changed. v pp v pplk - the third level offers a complete hardware protection against program and erase on all blocks. the protection status of each block can be set to locked, unlocked, and locked-down. table 14. , defines all of the possible protection states (wp , dq1, dq0), and appendix c. , figure 27. , shows a flowchart for the locking operations. reading a block?s lock status the lock status of every block can be read in the read electronic signature mode of the device. to enter this mode issue the read electronic signa- ture command. subsequent reads at the address specified in table 7. , will output the protection sta- tus of that block. the lock status is represented by dq0 and dq1. dq0 indicates the block lock/unlock status and is set by the lock command and cleared by the un- lock command. dq0 is automatically set when en- tering lock-down. dq1 indicates the lock-down status and is set by the lock-down command. dq1 cannot be cleared by software, only by a hardware reset or power-down. the following sections explain the operation of the locking system. locked state the default status of all blocks on power-up or af- ter a hardware reset is locked (states (0,0,1) or (1,0,1)). locked blocks are fully protected from program or erase operations. any program or erase operations attempted on a locked block will return an error in the status register. the status of a locked block can be changed to unlocked or locked-down using the appropriate software commands. an unlocked block can be locked by issuing the lock command. unlocked state unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. all unlocked blocks return to the locked state after a hardware reset or when the device is powered-down. the status of an unlocked block can be changed to locked or locked-down using the appropriate software commands. a locked block can be un- locked by issuing the unlock command. lock-down state blocks that are locked-down (state (0,1,x))are protected from program and erase operations (as for locked blocks) but their protection status can- not be changed using software commands alone. a locked or unlocked block can be locked-down by issuing the lock-down command. locked- down blocks revert to the locked state when the device is reset or powered-down. the lock-down function is dependent on the write protect, wp , input pin. when wp =0 (v il ), the blocks in the lock-down state (0,1,x) are protected from program, erase and protection status changes. when wp =1 (v ih ) the lock-down function is dis- abled (1,1,x) and locked-down blocks can be in- dividually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. when the lock-down function is disabled (wp =1) blocks can be locked (1,1,1) and unlocked (1,1,0) as desired. when wp =0 blocks that were previ- ously locked-down return to the lock-down state (0,1,x) regardless of any changes that were made while wp =1. device reset or power-down resets all blocks, in- cluding those in lock-down, to the locked state. locking operations during erase suspend changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. this is useful in the case when another block needs to be updated while an erase operation is in progress. to change block locking during an erase opera- tion, first write the erase suspend command, then check the status register until it indicates that the erase operation has been suspended. next write the desired lock command sequence to a block and the lock status will be changed. after complet- ing any desired lock, read, or program operations, resume the erase operation with the erase re- sume command. if a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. locking operations cannot be performed during a program suspend.
m30l0r7000t0, m30l0r7000b0 34/83 table 14. lock status note: 1. the lock status is defined by the write protect pin and by dq1 (?1? for a locked-down block) and dq0 (?1? for a locked b lock) as read in the read electronic signature command with a1 = v ih and a0 = v il . 2. all blocks are locked at power-up, so the default configuration is 001 or 101 according to wp status. 3. a wp transition to v ih on a locked block will restore the previous dq0 value, giving a 111 or 110. current protection status (1) (wp , dq1, dq0) next protection status (1) (wp , dq1, dq0) current state program/erase allowed after block lock command after block unlock command after block lock-down command after wp transition 1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0 1,0,1 (2) no 1,0,1 1,0,0 1,1,1 0,0,1 1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1 1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1 0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0 0,0,1 (2) no 0,0,1 0,0,0 0,1,1 1,0,1 0,1,1 no 0,1,1 0,1,1 0,1,1 1,1,1 or 1,1,0 (3)
35/83 m30l0r7000t0, m30l0r7000b0 program and erase times and endurance cycles the program and erase times and the number of program/ erase cycles per block are shown in ta- ble 15. in the m30l0r7000t0/b0 the maximum number of program/ erase cycles depends on the voltage supply used. table 15. program, erase times and endurance cycles note: 1. t a = ?40 to 85c; v dd = 1.7v to 2.0v; v ddq = 1.7v to 2.0v. 2. values are liable to change with the external system-level ov erhead (command sequence and status register polling execution). 3. excludes the time needed to execute the command sequence. 4. average on entire device. parameter condition min typ typical after 100k w/e cycles max unit v pp = v dd erase parameter block (16 kwords) preprogrammed 0.65 1 2.5 s not preprogrammed 0.8 2.5 s main block (64 kwords) preprogrammed 1.4 3 4 s not preprogrammed 1.8 4 s program (3) single cell word program 10 100 s buffer program 10 s single word word program 10 100 s buffer program 10 s buffer (32 words) (buffer program) 320 s main block (64 kwords) 640 ms suspend latency program 5 10 s erase 5 25 s program/erase cycles (per block) main blocks 100,000 cycles parameter blocks 100,000 cycles v pp = v pph erase parameter block (16 kwords) 0.7 2.5 s main block (64 kwords) 1.2 4 s program (3) single cell word program 10 100 s single word word program 10 100 s buffered enhanced factory program (4) 3.5 s buffer (32 words) word program 320 s buffered enhanced factory program (4) 100 s main block (64 kwords) word program 640 ms buffered enhanced factory program (4) 200 ms bank (8 mbits) word program 5 s buffered enhanced factory program (4) 1.6 s program/erase cycles (per block) main blocks 1000 cycles parameter blocks 2500 cycles
m30l0r7000t0, m30l0r7000b0 36/83 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 16. absolute maximum ratings note: 1. compliant with the jedec std j-std-020b (for small body, sn-pb or pb assembly), the st ecopack ? 7191395 specification, and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu. symbol parameter value unit min max t a ambient operating temperature ?25 85 c t bias temperature under bias ?25 85 c t stg storage temperature ?65 125 c t lead lead temperature during soldering (1) c v io input or output voltage ?0.5 3.8 v v dd supply voltage ?0.2 2.5 v v ddq input/output supply voltage ?0.2 2.5 v v pp program voltage ?0.2 14 v i o output short circuit current 100 ma t vpph time for v pp at v pph 100 hours
37/83 m30l0r7000t0, m30l0r7000b0 dc and ac parameters this section summarizes the operating measure- ment conditions, and the dc and ac characteris- tics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 17., operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when rely- ing on the quoted parameters. table 17. operating and ac measurement conditions figure 8. ac measurement i/o waveform figure 9. ac measurement load circuit table 18. capacitance note: sampled only, not 100% tested. parameter m30l0r7000t0, m30l0r7000b0 units 85 min max v dd supply voltage 1.7 2.0 v v ddq supply voltage 1.7 2.0 v v pp supply voltage (factory environment) 8.5 12.6 v v pp supply voltage (application environment) ?0.4 v ddq +0.4 v ambient operating temperature ?25 85 c load capacitance (c l ) 30 pf input rise and fall times 5 ns input pulse voltages 0 to v ddq v input and output timing ref. voltages v ddq /2 v ai06161 v ddq 0v v ddq /2 ai06162 v ddq c l c l includes jig capacitance 16.7k ? device under test 0.1f v dd 0.1f v ddq 16.7k ? symbol parameter test condition min max unit c in input capacitance v in = 0v 68pf c out output capacitance v out = 0v 812pf
m30l0r7000t0, m30l0r7000b0 38/83 table 19. dc characteristics - currents note: 1. sampled only, not 100% tested. 2. v dd dual operation current is the sum of read and program or erase currents. symbol parameter test condition min typ max unit i li input leakage current 0v v in v ddq 1 a i lo output leakage current 0v v out v ddq 1 a i dd1 supply current asynchronous read (f=6mhz) e = v il , g = v ih 10 15 ma supply current synchronous read (f=40mhz) 4 word 7 16 ma 8 word 10 18 ma 16 word 13 20 ma continuous 18 25 ma supply current synchronous read (f=54mhz) 4 word 16 18 ma 8 word 18 20 ma 16 word 21 25 ma continuous 22 27 ma i dd2 supply current (reset) rp = v ss 0.2v 25 70 a i dd3 supply current (standby) e = v dd 0.2v 25 70 a i dd4 supply current (automatic standby) e = v il , g = v ih 25 70 a i dd5 (1) supply current (program) v pp = v pph 815ma v pp = v dd 10 20 ma supply current (erase) v pp = v pph 815ma v pp = v dd 10 20 ma i dd6 (1,2) supply current (dual operations) program/erase in one bank, asynchronous read in another bank 20 35 ma program/erase in one bank, synchronous read in another bank 32 47 ma i dd7 (1) supply current program/ erase suspended (standby) e = v dd 0.2v 25 70 a i pp1 (1) v pp supply current (program) v pp = v pph 25ma v pp = v dd 0.2 5 a v pp supply current (erase) v pp = v pph 25ma v pp = v dd 0.2 5 a i pp2 v pp supply current (read) v pp v dd 0.2 5 a i pp3 (1) v pp supply current (standby) v pp v dd 0.2 5 a
39/83 m30l0r7000t0, m30l0r7000b0 table 20. dc characteristics - voltages symbol parameter test condition min typ max unit v il input low voltage ?0.5 0.4 v v ih input high voltage v ddq ?0.4 v ddq + 0.4 v v ol output low voltage i ol = 100a 0.1 v v oh output high voltage i oh = ?100a v ddq ?0.1 v v pp1 v pp program voltage-logic program, erase 1.1 1.8 3.3 v v pph v pp program voltage factory program, erase 8.5 9.0 12.6 v v pplk program or erase lockout 0.4 v v lko v dd lock voltage 1v v rph rp pin extended high voltage 3.3 v
m30l0r7000t0, m30l0r7000b0 40/83 figure 10. asynchronous random access read ac waveforms ai08311 tavav telqx tehqx tglqv tglqx tghqx dq0-dq15 e g telqv tehqz tghqz valid a0-a22 valid valid l tellh tllqv tlllh tavlh tlhax taxqx wait teltv tehtz note. write enable, w, is high, wait is active low. hi-z hi-z tavqv tgltv tghtz
41/83 m30l0r7000t0, m30l0r7000b0 figure 11. asynchronous page read ac waveforms ai08334 a2-a22 e g a0-a1 valid add. l dq0-dq15 valid add. valid add. valid address valid address valid data tlhax tavlh tllqv tavqv1 tglqx tlllh tellh wait tavav telqv telqx teltv tglqv (1) note 1. wait is active low. valid address latch outputs enabled valid data standby hi-z tgltv valid data valid data valid data
m30l0r7000t0, m30l0r7000b0 42/83 table 21. asynchronous read ac characteristics note: 1. sampled only, not 100% tested. 2. g may be delayed by up to t elqv - t glqv after the falling edge of e without increasing t elqv . symbol alt parameter m30l0r7000t0/b0 unit 85 read timings t avav t rc address valid to next address valid min 85 ns t avqv t acc address valid to output valid (random) max 85 ns t avqv1 t page address valid to output valid (page) max 25 ns t axqx (1) t oh address transition to output transition min 0 ns t eltv chip enable low to wait valid max 14 ns t elqv (2) t ce chip enable low to output valid max 85 ns t elqx (1) t lz chip enable low to output transition min 0 ns t ehtz chip enable high to wait hi-z max 17 ns t ehqx (1) t oh chip enable high to output transition min 0 ns t ehqz (1) t hz chip enable high to output hi-z max 17 ns t glqv (2) t oe output enable low to output valid max 20 ns t glqx (1) t olz output enable low to output transition min 0 ns t gltv output enable low to wait valid max 14 ns t ghqx (1) t oh output enable high to output transition min 0 ns t ghqz (1) t df output enable high to output hi-z max 17 ns t ghtz output enable high to wait hi-z max 17 ns latch timings t avlh t avadvh address valid to latch enable high min 7 ns t ellh t eladvh chip enable low to latch enable high min 10 ns t lhax t advhax latch enable high to address transition min 7 ns t lllh t advladvh latch enable pulse width min 7 ns t llqv t advlqv latch enable low to output valid (random) max 85 ns
43/83 m30l0r7000t0, m30l0r7000b0 figure 12. synchronous burst read ac waveforms ai10197 dq0-dq15 e g a0-a22 l wait k (4) valid valid valid address tlllh tavlh tglqx tavkh tllkh telkh tkhax not valid valid note 1 note 2 note 2 tkhtx tehqx tehqz tghqx tghqz hi-z valid note 2 teltv tkhtv tehtz address latch x latency valid data flow boundary crossing valid data standby note 1. the number of clock cycles to be inserted depends on the x latency set in the burst configuration register. 2. the wait signal can be configured to be active during wait state or one cycle before. wait signal is active low. 3. address latched and data output on the rising clock edge. 4. either the rising or the falling edge of the clock signal, k, can be configured as the active edge. here, the activ e edge of k is the rising one. tehel tkhqv tkhqx hi-z tgltv
m30l0r7000t0, m30l0r7000b0 44/83 figure 13. single synchronous read ac waveforms ai08312 e g a0-a22 l wait (1,2) k (2) valid address tglqv tavkh tllkh telkh hi-z telqx tkhqv note 1. the wait signal is configured to be active during wait state. wait signal is active low. 2. address latched and data output on the rising clock edge. either the rising or the falling edge of the clock signal , k, can be configured as the active edge. here, the active edge is the rising one. tglqx tkhtv dq0-dq15 valid hi-z telqv tgltv tghtz
45/83 m30l0r7000t0, m30l0r7000b0 figure 14. synchronous burst read suspend ac waveforms ai08308 dq0-dq15 e g a0-a22 l wait (2) k (4) valid valid valid address tlllh tavlh tglqv tavkh tllkh telkh tkhax not valid not valid note 1 tehqx tehqz tghqx tghqz hi-z teltv tkhqv tehtz note 1. the number of clock cycles to be inserted depends on the x latency set in the configuration register. 2. the wait signal is configured to be active during wait state. wait signal is active low. 3. the clock signal can be held high or low 4. address latched and data output on the rising clock edge. either the rising or the falling edge of the clock signal , k, can be configured as the active edge. here, the active edge is the rising one. tglqx tehel tghqz tglqv note 3 hi-z tgltv tghtz tgltv
m30l0r7000t0, m30l0r7000b0 46/83 figure 15. clock input ac waveform table 22. synchronous read ac characteristics note: 1. sampled only, not 100% tested. 2. for other timings please refer to table 21., asynchronous read ac characteristics . symbol alt parameter m30l0r7000t0/b0 unit 85 synchronous read timings t avkh t avclkh address valid to clock high min 7 ns t elkh t elclkh chip enable low to clock high min 7 ns t eltv chip enable low to wait valid max 14 ns t ehel chip enable pulse width (subsequent synchronous reads) min 14 ns t ehtz chip enable high to wait hi-z max 17 ns t khax t clkhax clock high to address transition min 7 ns t khqv t khtv t clkhqv clock high to output valid clock high to wait valid max 14 ns t khqx t khtx t clkhqx clock high to output transition clock high to wait transition min 3 ns t llkh t advlclkh latch enable low to clock high min 7 ns clock specifications t khkh t clk clock period (f=40mhz) min ns clock period (f=47mhz) min clock period (f=54mhz) min 18.5 ns t khkl t klkh clock high to clock low clock low to clock high min 3.5 ns t f t r clock fall or rise time max 3 ns ai06981 tkhkh tf tr tkhkl tklkh
47/83 m30l0r7000t0, m30l0r7000b0 figure 16. write ac waveforms, write enable controlled e g w dq0-dq15 command cmd or data status register v pp valid address a0-a22 tavav tqvvpl tavwh twhax program or erase telwl twheh twhdx tdvwh twlwh twhwl tvphwh set-up command confirm command or data input status register read 1st polling telqv ai08016 twphwh wp twhgl tqvwpl twhel bank address valid address l tavlh tlllh tellh tlhax tghwl twhqv twhwpl twhvpl telkv k twhll twhav
m30l0r7000t0, m30l0r7000b0 48/83 table 23. write ac characteristics, write enable controlled note: 1. sampled only, not 100% tested. 2. t whel has the values shown when reading in the targeted bank. system designers should take this into account and may insert a software no-op instruction to delay the first read in the same bank after issuing a command. if it is a read array operation in a different bank t whel is 0ns. 3. meaningful only if l is always kept low. symbol alt parameter m30l0r7000t0/b0 unit 85 write enable controlled timings t avav t wc address valid to next address valid min 85 ns t avlh address valid to latch enable high min 7 ns t avwh (3) address valid to write enable high min 50 ns t dvwh t ds data valid to write enable high min 50 ns t ellh chip enable low to latch enable high min 10 ns t elwl t cs chip enable low to write enable low min 0 ns t elqv chip enable low to output valid min 85 ns t elkv chip enable low to clock valid min 9 ns t ghwl output enable high to write enable low min 17 ns t lhax latch enable high to address transition min 9 ns t lllh latch enable pulse width min 9 ns t whav (3) write enable high to address valid min 0 ns t whax (3) t ah write enable high to address transition min 0 ns t whdx t dh write enable high to input transition min 0 ns t wheh t ch write enable high to chip enable high min 0 ns t whel (2) write enable high to chip enable low min 25 ns t whgl write enable high to output enable low min 0 ns t whll write enable high to latch enable low min 0 ns t whwl t wph write enable high to write enable low min 25 ns t whqv write enable high to output valid min 110 ns t wlwh t wp write enable low to write enable high min 50 ns protection timings t qvvpl output (status register) valid to v pp low min 0 ns t qvwpl output (status register) valid to write protect low min 0 ns t vphwh t vps v pp high to write enable high min 200 ns t whvpl write enable high to v pp low min 200 ns t whwpl write enable high to write protect low min 200 ns t wphwh write protect high to write enable high min 200 ns
49/83 m30l0r7000t0, m30l0r7000b0 figure 17. write ac waveforms, chip enable controlled w g e dq0-dq15 command cmd or data status register v pp valid address a0-a22 tavav tqvvpl taveh tehax program or erase twlel tehwh tehdx tdveh teleh tehel tvpheh set-up command confirm command or data input status register read 1st polling telqv ai08017 twpheh wp tehgl tqvwpl twhel bank address valid address l tavlh tlllh tlhax tghel tehwpl tehvpl telkv k tellh twhqv
m30l0r7000t0, m30l0r7000b0 50/83 table 24. write ac characteristics, chip enable controlled note: 1. sampled only, not 100% tested. 2. t whel has the values shown when reading in the targeted bank. system designers should take this into account and may insert a software no-op instruction to delay the first read in the same bank after issuing a command. if it is a read array operation in a different bank t whel is 0ns. symbol alt parameter m30l0r7000t0/b0 unit 85 chip enable controlled timings t avav t wc address valid to next address valid min 85 ns t aveh address valid to chip enable high min 50 ns t avlh address valid to latch enable high min 7 ns t dveh t ds data valid to write enable high min 50 ns t ehax t ah chip enable high to address transition min 0 ns t ehdx t dh chip enable high to input transition min 0 ns t ehel t cph chip enable high to chip enable low min 25 ns t ehgl chip enable high to output enable low min 0 ns t ehwh t ch chip enable high to write enable high min 0 ns t elkv chip enable low to clock valid min 9 ns t eleh t cp chip enable low to chip enable high min 50 ns t ellh chip enable low to latch enable high min 10 ns t elqv chip enable low to output valid min 85 ns t ghel output enable high to chip enable low min 17 ns t lhax latch enable high to address transition min 9 ns t lllh latch enable pulse width min 9 ns t whel (2) write enable high to chip enable low min 25 ns t whqv write enable high to output valid min 110 ns t wlel t cs write enable low to chip enable low min 0 ns protection timings t ehvpl chip enable high to v pp low min 200 ns t ehwpl chip enable high to write protect low min 200 ns t qvvpl output (status register) valid to v pp low min 0 ns t qvwpl output (status register) valid to write protect low min 0 ns t vpheh t vps v pp high to chip enable high min 200 ns t wpheh write protect high to chip enable high min 200 ns
51/83 m30l0r7000t0, m30l0r7000b0 figure 18. reset and power-up ac waveforms table 25. reset and power-up ac characteristics note: 1. the device reset is possible but not guaranteed if t plph < 50ns. 2. sampled only, not 100% tested. 3. it is important to assert rp in order to allow proper cpu initialization during power-up or reset. symbol parameter test condition 85 unit t plwl t plel t plgl t plll reset low to write enable low, chip enable low, output enable low, latch enable low during program min 10 s during erase min 25 s other conditions min 80 ns t phwl t phel t phgl t phll reset high to write enable low chip enable low output enable low latch enable low min 30 ns t plph (1,2) rp pulse width min 50 ns t vdhph (3) supply voltages high to reset high min 50 s ai06976 w, rp e, g, vdd, vddq tvdhph tplph power-up reset tplwl tplel tplgl tplll l tphwl tphel tphgl tphll
m30l0r7000t0, m30l0r7000b0 52/83 package mechanical figure 19. tfbga88 8x10mm - 8x10 ball array, 0.8mm pitch, bottom view package outline note: drawing is not to scale. table 26. tfbga88 8x10mm - 8x10 ball array, 0.8mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.200 0.0079 a2 0.850 0.0335 b 0.350 0.300 0.400 0.0138 0.0118 0.0157 d 8.000 7.900 8.100 0.3150 0.3110 0.3189 d1 5.600 0.2205 ddd 0.100 0.0039 e 10.000 9.900 10.100 0.3937 0.3898 0.3976 e1 7.200 0.2835 e2 8.800 0.3465 e 0.800 ? ? 0.0315 ? ? fd 1.200 0.0472 fe 1.400 0.0551 fe1 0.600 0.0236 sd 0.400 0.0157 se 0.400 0.0157 a2 a1 a bga-z42 ddd d e e b se fd e2 d1 sd ball "a1" e1 fe fe1
53/83 m30l0r7000t0, m30l0r7000b0 figure 20. tfbga88 daisy chain - package connections (top view through package) ai08304 d c b a 8 7 6 5 4 3 2 1 g f e j h m l k
m30l0r7000t0, m30l0r7000b0 54/83 figure 21. tfbga88 daisy chain - pcb connection proposal (top view through package) ai08305 d c b a 8 7 6 5 4 3 2 1 g f e j h m l k end point start point
55/83 m30l0r7000t0, m30l0r7000b0 part numbering table 27. ordering information scheme example: m30 l 0 r 7 0 0 0 t 0 zaq t device type m30 = multiple flash memory product flash device identifier 1 l = multilevel, multiple bank, burst mode flash device identifier 2 0 = no other architecture operating voltage r = v dd = v ddq = 1.8v typical flash 1 density 7 = 128 mbit flash 2 density 0 = no die flash 3 density 0 = no die flash 4 density 0 = no die parameter block location t = top boot block b = bottom boot block product version 0 = flash 0.13m, 85ns package zaq = tfbga88 8 x 10mm, 0.80mm pitch, quadruple stacked footprint option blank = standard packing t = tape & reel packing e = lead-free and rohs package, standard packing f = lead-free and rohs package, tape & reel packing
m30l0r7000t0, m30l0r7000b0 56/83 table 28. daisy chain ordering scheme devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the st sales office nearest to you. example: m30l0r7000 -zaq t device type m30l0r7000t0 daisy chain zaq = lfbga88 8 x 10mm, 0.80mm pitch, quadruple stacked footprint option blank = standard packing t = tape & reel packing e = lead-free and rohs package, standard packing f = lead-free and rohs package, tape & reel packing
57/83 m30l0r7000t0, m30l0r7000b0 appendix a. block address tables table 29. top boot block addresses, m30l0r7000t0 bank # size (kword) address range parameter bank 0 16 7fc000-7fffff 1 16 7f8000-7fbfff 2 16 7f4000-7f7fff 3 16 7f0000-7f3fff 4 64 7e0000-7effff 5 64 7d0000-7dffff 6 64 7c0000-7cffff 7 64 7b0000-7bffff 8 64 7a0000-7affff 9 64 790000-79ffff 10 64 780000-78ffff bank 1 11 64 770000-77ffff 12 64 760000-76ffff 13 64 750000-75ffff 14 64 740000-74ffff 15 64 730000-73ffff 16 64 720000-72ffff 17 64 710000-71ffff 18 64 700000-70ffff bank 2 19 64 6f0000-6fffff 20 64 6e0000-6effff 21 64 6d0000-6dffff 22 64 6c0000-6cffff 23 64 6b0000-6bffff 24 64 6a0000-6affff 25 64 690000-69ffff 26 64 680000-68ffff bank 3 27 64 670000-67ffff 28 64 660000-66ffff 29 64 650000-65ffff 30 64 640000-64ffff 31 64 630000-63ffff 32 64 620000-62ffff 33 64 610000-61ffff 34 64 600000-60ffff bank 4 35 64 5f0000-5fffff 36 64 5e0000-5effff 37 64 5d0000-5dffff 38 64 5c0000-5cffff 39 64 5b0000-5bffff 40 64 5a0000-5affff 41 64 590000-59ffff 42 64 580000-58ffff bank 5 43 64 570000-57ffff 44 64 560000-56ffff 45 64 550000-55ffff 46 64 540000-54ffff 47 64 530000-53ffff 48 64 520000-52ffff 49 64 510000-51ffff 50 64 500000-50ffff bank 6 51 64 4f0000-4fffff 52 64 4e0000-4effff 53 64 4d0000-4dffff 54 64 4c0000-4cffff 55 64 4b0000-4bffff 56 64 4a0000-4affff 57 64 490000-49ffff 58 64 480000-48ffff bank 7 59 64 470000-47ffff 60 64 460000-46ffff 61 64 450000-45ffff 62 64 440000-44ffff 63 64 430000-43ffff 64 64 420000-42ffff 65 64 410000-41ffff 66 64 400000-40ffff bank 8 67 64 3f0000-3fffff 68 64 3e0000-3effff 69 64 3d0000-3dffff 70 64 3c0000-3cffff 71 64 3b0000-3bffff 72 64 3a0000-3affff 73 64 390000-39ffff 74 64 380000-38ffff
m30l0r7000t0, m30l0r7000b0 58/83 note: there are two bank regions: bank region 1 contains all the banks that are made up of main blocks only; bank region 2 contains the banks that are made up of the parameter and main blocks (parameter bank). bank 9 75 64 370000-37ffff 76 64 360000-36ffff 77 64 350000-35ffff 78 64 340000-34ffff 79 64 330000-33ffff 80 64 320000-32ffff 81 64 310000-31ffff 82 64 300000-30ffff bank 10 83 64 2f0000-2fffff 84 64 2e0000-2effff 85 64 2d0000-2dffff 86 64 2c0000-2cffff 87 64 2b0000-2bffff 88 64 2a0000-2affff 89 64 290000-29ffff 90 64 280000-28ffff bank 11 91 64 270000-27ffff 92 64 260000-26ffff 93 64 250000-25ffff 94 64 240000-24ffff 95 64 230000-23ffff 96 64 220000-22ffff 97 64 210000-21ffff 98 64 200000-20ffff bank 12 99 64 1f0000-1fffff 100 64 1e0000-1effff 101 64 1d0000-1dffff 102 64 1c0000-1cffff 103 64 1b0000-1bffff 104 64 1a0000-1affff 105 64 190000-19ffff 106 64 180000-18ffff bank 13 107 64 170000-17ffff 108 64 160000-16ffff 109 64 150000-15ffff 110 64 140000-14ffff 111 64 130000-13ffff 112 64 120000-12ffff 113 64 110000-11ffff 114 64 100000-10ffff bank 14 115 64 0f0000-0fffff 116 64 0e0000-0effff 117 64 0d0000-0dffff 118 64 0c0000-0cffff 119 64 0b0000-0bffff 120 64 0a0000-0affff 121 64 090000-09ffff 122 64 080000-08ffff bank 15 123 64 070000-07ffff 124 64 060000-06ffff 125 64 050000-05ffff 126 64 040000-04ffff 127 64 030000-03ffff 128 64 020000-02ffff 129 64 010000-01ffff 130 64 000000-00ffff
59/83 m30l0r7000t0, m30l0r7000b0 table 30. bottom boot block addresses, m30l0r7000b0 bank # size (kword) address range bank 15 130 64 7f0000-7fffff 129 64 7e0000-7effff 128 64 7d0000-7dffff 127 64 7c0000-7cffff 126 64 7b0000-7bffff 125 64 7a0000-7affff 124 64 790000-79ffff 123 64 780000-78ffff bank 14 122 64 770000-77ffff 121 64 760000-76ffff 120 64 750000-75ffff 119 64 740000-74ffff 118 64 730000-73ffff 117 64 720000-72ffff 116 64 710000-71ffff 115 64 700000-70ffff bank 13 114 64 6f0000-6fffff 113 64 6e0000-6effff 112 64 6d0000-6dffff 111 64 6c0000-6cffff 110 64 6b0000-6bffff 109 64 6a0000-6affff 108 64 690000-69ffff 107 64 680000-68ffff bank 12 106 64 670000-67ffff 105 64 660000-66ffff 104 64 650000-65ffff 103 64 640000-64ffff 102 64 630000-63ffff 101 64 620000-62ffff 100 64 610000-61ffff 99 64 600000-60ffff bank 11 98 64 5f0000-5fffff 97 64 5e0000-5effff 96 64 5d0000-5dffff 95 64 5c0000-5cffff 94 64 5b0000-5bffff 93 64 5a0000-5affff 92 64 590000-59ffff 91 64 580000-58ffff bank 10 90 64 570000-57ffff 89 64 560000-56ffff 88 64 550000-55ffff 87 64 540000-54ffff 86 64 530000-53ffff 85 64 520000-52ffff 84 64 510000-51ffff 83 64 500000-50ffff bank 9 82 64 4f0000-4fffff 81 64 4e0000-4effff 80 64 4d0000-4dffff 79 64 4c0000-4cffff 78 64 4b0000-4bffff 77 64 4a0000-4affff 76 64 490000-49ffff 75 64 480000-48ffff bank 8 74 64 470000-47ffff 73 64 460000-46ffff 72 64 450000-45ffff 71 64 440000-44ffff 70 64 430000-43ffff 69 64 420000-42ffff 68 64 410000-41ffff 67 64 400000-40ffff bank 7 66 64 3f0000-3fffff 65 64 3e0000-3effff 64 64 3d0000-3dffff 63 64 3c0000-3cffff 62 64 3b0000-3bffff 61 64 3a0000-3affff 60 64 390000-39ffff 59 64 380000-38ffff bank 6 58 64 370000-37ffff 57 64 360000-36ffff 56 64 350000-35ffff 55 64 340000-34ffff 54 64 330000-33ffff 53 64 320000-32ffff 52 64 310000-31ffff 51 64 300000-30ffff
m30l0r7000t0, m30l0r7000b0 60/83 note: there are two bank regions: bank region 2 contains all the banks that are made up of main blocks only; bank region 1 contains the banks that are made up of the parameter and main blocks (parameter bank). bank 5 50 64 2f0000-2fffff 49 64 2e0000-2effff 48 64 2d0000-2dffff 47 64 2c0000-2cffff 46 64 2b0000-2bffff 45 64 2a0000-2affff 44 64 290000-29ffff 43 64 280000-28ffff bank 4 42 64 270000-27ffff 41 64 260000-26ffff 40 64 250000-25ffff 39 64 240000-24ffff 38 64 230000-23ffff 37 64 220000-22ffff 36 64 210000-21ffff 35 64 200000-20ffff bank 3 34 64 1f0000-1fffff 33 64 1e0000-1effff 32 64 1d0000-1dffff 31 64 1c0000-1cffff 30 64 1b0000-1bffff 29 64 1a0000-1affff 28 64 190000-19ffff 27 64 180000-18ffff bank 2 26 64 170000-17ffff 25 64 160000-16ffff 24 64 150000-15ffff 23 64 140000-14ffff 22 64 130000-13ffff 21 64 120000-12ffff 20 64 110000-11ffff 19 64 1f0000-1fffff bank 1 18 64 0f0000-0fffff 17 64 0e0000-0effff 16 64 0d0000-0dffff 15 64 0c0000-0cffff 14 64 0b0000-0bffff 13 64 0a0000-0affff 12 64 090000-09ffff 11 64 080000-08ffff parameter bank 10 64 070000-07ffff 9 64 060000-06ffff 8 64 050000-05ffff 7 64 040000-04ffff 6 64 030000-03ffff 5 64 020000-02ffff 4 64 010000-01ffff 3 16 00c000-00ffff 2 16 008000-00bfff 1 16 004000-007fff 0 16 000000-003fff
61/83 m30l0r7000t0, m30l0r7000b0 appendix b. common flash interface the common flash interface is a jedec ap- proved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory. the system can interface easily with the de- vice, enabling the software to upgrade itself when necessary. when the read cfi query command is issued the device enters cfi query mode and the data structure is read from the memory. tables 31 , 32 , 33 , 34 , 35 , 36 , 37 , 38 , 39 and 40 show the ad- dresses used to retrieve the data. the query data is always presented on the lowest order data out- puts (dq0-dq7), the other outputs (dq8-dq15) are set to 0. the cfi data structure also contains a security area where a 64 bit unique security number is writ- ten (see figure 5., protection register memory map ). this area can be accessed only in read mode by the final user. it is impossible to change the security number after it has been written by st. issue a read array command to return to read mode. table 31. query structure overview note: the flash memory display the cfi data structure when cfi query command is issued. in this table are listed the main sub-se ctions detailed in tables 32 , 33 , 34 , and 35 . query data is always presented on the lowest order data outputs. table 32. cfi query identification string offset sub-section name description 000h reserved reserved for algorithm-specific information 010h cfi query identification string command set id and algorithm data offset 01bh system interface information device timing & voltage information 027h device geometry definition flash device layout p primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) 080h security code area lock protection register unique device number and user programmable otp offset sub-section name description value 000h 0020h manufacturer code st 001h 88c4h 88c5h device code to p bottom 002h reserved reserved 003h reserved reserved 004h-00fh reserved reserved 010h 0051h query unique ascii string "qry" "q" 011h 0052h "r" 012h 0059h "y" 013h 0003h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm 014h 0000h 015h offset = p = 000ah address for primary algorithm extended query table (see table 34. ) p = 10ah 016h 0001h 017h 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported na 018h 0000h 019h value = a = 0000h address for alternate algorithm extended query table na 01ah 0000h
m30l0r7000t0, m30l0r7000b0 62/83 table 33. cfi query system interface information offset data description value 01bh 0017h v dd logic supply minimum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 1.7v 01ch 0020h v dd logic supply maximum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 2v 01dh 0085h v pp [programming] supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts 8.5v 01eh 0095h v pp [programming] supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts 9.5v 01fh 0004h typical time-out per single byte/word program = 2 n s 16s 020h 0009h typical time-out for buffer program = 2 n s 512s 021h 000bh typical time-out per individual block erase = 2 n ms 2s 022h 0000h typical time-out for full chip erase = 2 n ms na 023h 0003h maximum time-out for word program = 2 n times typical 128s 024h 0001h maximum time-out for buffer program = 2 n times typical 1024s 025h 0001h maximum time-out per individual block erase = 2 n times typical 4s 026h 0000h maximum time-out for chip erase = 2 n times typical na
63/83 m30l0r7000t0, m30l0r7000b0 table 34. device geometry definition offset word mode data description value 027h 0018h device size = 2 n in number of bytes 16 mbytes 028h 029h 0001h 0000h flash device interface code description x16 async. 02ah 02bh 0006h 0000h maximum number of bytes in multi-byte program or page = 2 n 64 bytes 02ch 0002h number of identical sized erase block regions within the device bit 7 to 0 = x = number of erase block regions 2 m30l0r7000t0 02dh 02eh 007eh 0000h region 1 information number of identical-size erase blocks = 007eh+1 127 02fh 030h 0000h 0002h region 1 information block size in region 1 = 0200h * 256 byte 128 kbyte 031h 032h 0003h 0000h region 2 information number of identical-size erase blocks = 0003h+1 4 033h 034h 0080h 0000h region 2 information block size in region 2 = 0080h * 256 byte 32 kbyte 035h 038h reserved reserved for future erase block region information na m30l0r7000b0 02dh 02eh 0003h 0000h region 1 information number of identical-size erase block = 0003h+1 4 02fh 030h 0080h 0000h region 1 information block size in region 1 = 0080h * 256 bytes 32 kbytes 031h 032h 007eh 0000h region 2 information number of identical-size erase block = 007eh+1 127 033h 034h 0000h 0002h region 2 information block size in region 2 = 0200h * 256 bytes 128 kbytes 035h 038h reserved reserved for future erase block region information na
m30l0r7000t0, m30l0r7000b0 64/83 table 35. primary algorithm-specific extended query table offset data description value (p)h = 10ah 0050h primary algorithm extended query table unique ascii string ?pri? "p" 0052h "r" 0049h "i" (p+3)h = 10dh 0031h major version number, ascii "1" (p+4)h = 10eh 0033h minor version number, ascii "3" (p+5)h = 10fh 00e6h extended query table contents for primary algorithm. address (p+5)h contains less significant byte. bit 0 chip erase supported (1 = yes, 0 = no) bit 1 erase suspend supported (1 = yes, 0 = no) bit 2 program suspend supported (1 = yes, 0 = no) bit 3 legacy lock/unlock supported (1 = yes, 0 = no) bit 4 queued erase supported (1 = yes, 0 = no) bit 5 instant individual block locking supported (1 = yes, 0 = no) bit 6 protection bits supported (1 = yes, 0 = no) bit 7 page mode read supported (1 = yes, 0 = no) bit 8 synchronous read supported (1 = yes, 0 = no) bit 9 simultaneous operation supported (1 = yes, 0 = no) bit 10 to 31reserved; undefined bits are ?0?. if bit 31 is ?1? then another 31 bit field of optional features follows at the end of the bit-30 field. no yes yes no no yes yes yes yes yes 0003h (p+7)h = 111h 0000h (p+8)h = 112h 0000h (p+9)h = 113h 0001h supported functions after suspend read array, read status register and cfi query bit 0 program supported after erase suspend (1 = yes, 0 = no) bit 7 to 1 reserved; undefined bits are ?0? yes (p+a)h = 114h 0003h block protect status defines which bits in the block status register section of the query are implemented. bit 0 block protect status register lock/unlock bit active (1 = yes, 0 = no) bit 1 block lock status register lock-down bit active (1 = yes, 0 = no) bit 15 to 2 reserved for future use; undefined bits are ?0? yes yes (p+b)h = 115h 0000h (p+c)h = 116h 0018h v dd logic supply optimum program/erase voltage (highest performance) bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 1.8v (p+d)h = 117h 0090h v pp supply optimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 9v
65/83 m30l0r7000t0, m30l0r7000b0 table 36. protection register information table 37. burst read information offset data description value (p+e)h = 118h 0002h number of protection register fields in jedec id space. 0000h indicates that 256 fields are available. 2 (p+f)h = 119h 0080h protection field 1: protection description bits 0-7 lower byte of protection register address bits 8-15 upper byte of protection register address bits 16-23 2 n bytes in factory pre-programmed region bits 24-31 2 n bytes in user programmable region 80h (p+10)h = 11ah 0000h 00h (p+11)h = 11bh 0003h 8 bytes (p+12)h = 11ch 0003h 8 bytes (p+13)h = 11dh 0089h protection register 2: protection description bits 0-31 protection register address bits 32-39 n number of factory programmed regions (lower byte) bits 40-47 n number of factory programmed regions (upper byte) bits 48-55 2 n bytes in factory programmable region bits 56-63 n number of user programmable regions (lower byte) bits 64-71 n number of user programmable regions (upper byte) bits 72-79 2 n bytes in user programmable region 89h (p+14)h = 11eh 0000h 00h (p+15)h = 11fh 0000h 00h (p+16)h = 120h 0000h 00h (p+17)h = 121h 0000h 0 (p+18)h = 122h 0000h 0 (p+19)h = 123h 0000h 0 (p+1a)h = 124h 0010h 16 (p+1b)h = 125h 0000h 0 (p+1c)h = 126h 0004h 16 offset data description value (p+1d)h = 127h 0003h page-mode read capability bits 0-7 ?n? such that 2 n hex value represents the number of read- page bytes. see offset 28h for device word width to determine page-mode data output width. 8 bytes (p+1e)h = 128h 0004h number of synchronous mode read configuration fields that follow. 4 (p+1f)h = 129h 0001h synchronous mode read capability configuration 1 bit 3-7 reserved bit 0-2 ?n? such that 2 n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. a value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device?s burstable address space. this field?s 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. see offset 28h for word width to determine the burst data output width. 4 (p+20)h = 12ah 0002h synchronous mode read capability configuration 2 8 (p-21)h = 12bh (p+22)h = 12ch 0003h 0007h synchronous mode read capability configuration 3 16 synchronous mode read capability configuration 4 cont.
m30l0r7000t0, m30l0r7000b0 66/83 table 38. bank and erase block region information note: 1. the variable p is a pointer which is defined at cfi offset 15h. 2. bank regions. there are two bank regions, see table 29. and table 30. table 39. bank and erase block region 1 information flash memory (top) flash memory (bottom) description offset data offset data (p+23)h = 12dh 02h (p+23)h = 12dh 02h number of bank regions within the device flash memory (top) flash memory (bottom) description offset data offset data (p+24)h = 12eh 0fh (p+24)h = 12eh 01h number of identical banks within bank region 1 (p+25)h = 12fh 00h (p+25)h = 12fh 00h (p+26)h = 130h 11h (p+26)h = 130h 11h number of program or erase operations allowed in bank region 1: bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+27)h = 131h 00h (p+27)h = 131h 00h number of program or erase operations allowed in other banks while a bank in same region is programming bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+28)h = 132h 00h (p+28)h = 132h 00h number of program or erase operations allowed in other banks while a bank in this region is erasing bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+29)h = 133h 01h (p+29)h = 133h 02h types of erase block regions in bank region 1 n = number of erase block regions with contiguous same-size erase blocks. symmetrically blocked banks have one blocking region (2) . (p+2a)h = 134h 77h (p+2a)h = 134h 03h bank region 1 erase block type 1 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = number of bytes in erase block region (p+2b)h = 135h 00h (p+2b)h = 135h 00h (p+2c)h = 136h 00h (p+2c)h = 136h 80h (p+2d)h = 137h 02h (p+2d)h = 137h 00h (p+2e)h = 138h 64h (p+2e)h = 138h 64h bank region 1 (erase block type 1) minimum block erase cycles 1000 (p+2f)h = 139h 00h (p+2f)h = 139h 00h (p+30)h = 13ah 02h (p+30)h = 13ah 02h bank region 1 (erase block type 1): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved (p+31)h = 13bh 03h (p+31)h = 13bh 03h bank region 1 (erase block type 1): page mode and synchronous mode capabilities bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved
67/83 m30l0r7000t0, m30l0r7000b0 note: 1. the variable p is a pointer which is defined at cfi offset 15h. 2. bank regions. there are two bank regi ons, there are two bank regions, see table 29. and table 30. table 40. bank and erase block region 2 information (p+32)h = 13ch 06h bank region 1 erase block type 2 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = number of bytes in erase block region (p+33)h = 13dh 00h (p+34)h = 13eh 00h (p+35)h = 13fh 02h (p+36)h = 140h 64h bank region 1 (erase block type 2) minimum block erase cycles 1000 (p+37)h = 141h 00h (p+38)h = 142h 02h bank regions 1 (erase block type 2): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved (p+39)h = 143h 03h bank region 1 (erase block type 2): page mode and synchronous mode capabilities bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved flash memory (top) flash memory (bottom) description offset data offset data (p+32)h = 13ch 01h (p+3a)h = 144h 0fh number of identical banks within bank region 2 (p+33)h = 13dh 00h (p+3b)h = 145h 00h (p+34)h = 13eh 11h (p+3c)h = 146h 11h number of program or erase operations allowed in bank region 2: bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+35)h = 13fh 00h (p+3d)h = 147h 00h number of program or erase operations allowed in other banks while a bank in this region is programming bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+36)h = 140h 00h (p+3e)h = 148h 00h number of program or erase operations allowed in other banks while a bank in this region is erasing bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+37)h = 141h 02h (p+3f)h = 149h 01h types of erase block regions in bank region 2 n = number of erase block regions with contiguous same-size erase blocks. symmetrically blocked banks have one blocking region. (2) (p+38)h = 142h 06h (p+40)h = 14ah 77h bank region 2 erase block type 1 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = number of bytes in erase block region (p+39)h = 143h 00h (p+41)h = 14bh 00h (p+3a)h = 144h 00h (p+42)h = 14ch 00h (p+3b)h = 145h 02h (p+43)h = 14dh 02h flash memory (top) flash memory (bottom) description offset data offset data
m30l0r7000t0, m30l0r7000b0 68/83 note: 1. the variable p is a pointer which is defined at cfi offset 15h. 2. bank regions. there are two bank regi ons, there are two bank regions, see table 29. and table 30. (p+3c)h = 146h 64h (p+44)h = 14eh 64h bank region 2 (erase block type 1) minimum block erase cycles 1000 (p+3d)h = 147h 00h (p+45)h = 14fh 00h (p+3e)h = 148h 02h (p+46)h = 150h 02h bank region 2 (erase block type 1): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved (p+3f)h = 149h 03h (p+47)h = 151h 03h bank region 2 (erase block type 1):page mode and synchronous mode capabilities (defined in table 37. ) bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved (p+40)h = 14ah 03h bank region 2 erase block type 2 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = number of bytes in erase block region (p+41)h = 14bh 00h (p+42)h = 14ch 80h (p+43)h = 14dh 00h (p+44)h =14eh 64h bank region 2 (erase block type 2) minimum block erase cycles 1000 (p+45)h = 14fh 00h (p+46)h = 150h 02h bank region 2 (erase block type 2): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved (p+47)h = 151h 03h bank region 2 (erase block type 2): page mode and synchronous mode capabilities (defined in table 37. ) bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved (p+48)h = 152h (p+48)h = 152h feature space definitions (p+49)h = 153h (p+43)h = 153h reserved flash memory (top) flash memory (bottom) description offset data offset data
69/83 m30l0r7000t0, m30l0r7000b0 appendix c. flowcharts and pseudo codes figure 22. program flowchart and pseudo code note: 1. status check of sr1 (protected block), sr3 (v pp invalid) and sr4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase controller operations. 3. any address within the bank can equally be used. write 40h or 10h (3) ai06170b start write address & data read status register (3) yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) program_command (addresstoprogram, datatoprogram) {: writetoflash (addresstoprogram, 0x40); /*writetoflash (addresstoprogram, 0x10);*/ /*see note (3)*/ do { status_register=readflash (addresstoprogram); "see note (3)"; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr3==1) /*v pp invalid error */ error_handler ( ) ; yes end yes no sr1 = 0 program to protected block error (1, 2) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; }
m30l0r7000t0, m30l0r7000b0 70/83 figure 23. buffer program flowchart and pseudo code buffer program e8h command, start address ai08913b start write buffer data, start address yes x = n end no write n (1) , start address x = 0 write next buffer data, next program address x = x + 1 program buffer to flash confirm d0h read status register no sr7 = 1 yes full status register check (3) (2) read status register no sr7 = 1 yes buffer_program_command (start_address, n, buffer_program[] ) /* buffer_program [] is an array structure used to store the address and data to be programmed to the flash memory (the address must be within the segment start address and start address+n) */ { do {writetoflash ( start _address, 0xe8) ; status_register=readflash ( start _address); } while (status_register.sr7==0); writetoflash ( start _address, n); writetoflash (buffer_program[0].address, buffer_program[0].data); /*buffer_program[0].address is the start address*/ x = 0; while (x 71/83 m30l0r7000t0, m30l0r7000b0 figure 24. program suspend & resume flowchart and pseudo code note: the read status register command (write 70h) can be issued just before or just after the program resume command. write 70h ai10117b read status register yes no sr7 = 1 yes no sr2 = 1 write d0h read data from another address start write b0h program complete write ffh program_suspend_command ( ) { writetoflash (any_address, 0xb0) ; writetoflash (bank_address, 0x70) ; /* read status register to check if program has already completed */ do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr2==0) /*program completed */ { writetoflash (bank_address, 0xff) ; read_data ( ) ; /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (bank_address, 0xff) ; read_data ( ); /*read data from another address*/ writetoflash (any_address, 0xd0) ; /*write 0xd0 to resume program*/ writetoflash (bank_address, 0x70) ; /*read status register to check if program has completed */ } } write ffh program continues with bank in read status register mode read data write 70h (1)
m30l0r7000t0, m30l0r7000b0 72/83 figure 25. block erase flowchart and pseudo code note: 1. if an error is found, the status register must be cleared before further program/erase operations. 2. any address within the bank can equally be used. write 20h (2) ai10524 start write block address & d0h read status register (2) yes no sr7 = 1 yes no sr3 = 0 yes sr4, sr5 = 1 v pp invalid error (1) command sequence error (1) no no sr5 = 0 erase error (1) end yes no sr1 = 0 erase to protected block error (1) yes erase_command ( blocktoerase ) { writetoflash (blocktoerase, 0x20) ; /*see note (2) */ writetoflash (blocktoerase, 0xd0) ; /* only a12-a22 are significant */ /* memory enters read status state after the erase command */ } while (status_register.sr7== 0) ; do { status_register=readflash (blocktoerase) ; /* see note (2) */ /* e or g must be toggled*/ if (status_register.sr3==1) /*v pp invalid error */ error_handler ( ) ; if ( (status_register.sr4==1) && (status_register.sr5==1) ) /* command sequence error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; if ( (status_register.sr5==1) ) /* erase error */ error_handler ( ) ; }
73/83 m30l0r7000t0, m30l0r7000b0 figure 26. erase suspend & resume flowchart and pseudo code note: the read status register command (write 70h) can be issued just before or just after the erase resume command. write 70h ai10116b read status register yes no sr7 = 1 yes no sr6 = 1 erase continues with bank in read status register mode write d0h read data from another block or program/protection register program or block lock/unlock/lock-down start write b0h erase complete write ffh read data write ffh erase_suspend_command ( ) { writetoflash (bank_address, 0xb0) ; writetoflash (bank_address, 0x70) ; /* read status register to check if erase has already completed */ do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr6==0) /*erase completed */ { writetoflash (bank_address, 0xff) ; read_data ( ) ; /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (bank_address, 0xff) ; read_program_data ( ); /*read or program data from another block*/ writetoflash (bank_address, 0xd0) ; /*write 0xd0 to resume erase*/ writetoflash (bank_address, 0x70) ; /*read status register to check if erase has completed */ } } write 70h (1)
m30l0r7000t0, m30l0r7000b0 74/83 figure 27. locking operations flowchart and pseudo code note: 1. any address within the bank can equally be used. write 01h, d0h or 2fh ai06176b read block lock states yes no locking change confirmed? start write 60h (1) locking_operation_command (address, lock_operation) { writetoflash (address, 0x60) ; /*configuration setup*/ /* see note (1) */ if (readflash (address) ! = locking_state_expected) error_handler () ; /*check the locking state (see read block signature table )*/ writetoflash (address, 0xff) ; /*reset to read array mode*/ /*see note (1) */ } write ffh (1) write 90h (1) end if (lock_operation==lock) /*to protect the block*/ writetoflash (address, 0x01) ; else if (lock_operation==unlock) /*to unprotect the block*/ writetoflash (address, 0xd0) ; else if (lock_operation==lock-down) /*to lock the block*/ writetoflash (address, 0x2f) ; writetoflash (address, 0x90) ; /*see note (1) */
75/83 m30l0r7000t0, m30l0r7000b0 figure 28. protection register program flowchart and pseudo code note: 1. status check of sr1 (protected block), sr3 (v pp invalid) and sr4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program/erase controller operations. 3. any address within the bank can equally be used. write c0h (3) ai06177b start write address & data read status register (3) yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) protection_register_program_command (addresstoprogram, datatoprogram) {: writetoflash (addresstoprogram, 0xc0) ; /*see note (3) */ do { status_register=readflash (addresstoprogram) ; /* see note (3) */ /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr3==1) /*vpp invalid error */ error_handler ( ) ; yes end yes no sr1 = 0 program to protected block error (1, 2) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; }
m30l0r7000t0, m30l0r7000b0 76/83 figure 29. buffer enhanced factory program flowchart and pseudo code write 80h to address wa1 ai07302b start write d0h to address wa1 write ffffh to address = not wa1 read status register sr7 = 0 no no sr0 = 0 yes read status register sr3 and sr1for errors exit write pdx address wa1 increment count x = x + 1 initialize count x = 0 x = 32 yes read status register last data? yes read status register sr7 = 1 yes full status register check end yes buffer_enhanced_factory_program_command (start_address, dataflow[]) { writetoflash (start_address, 0x80) ; writetoflash (start_address, 0xd0) ; do{ do { status_register = readflash (start_address); if (status_register.sr4==1) { /*error*/ if (status_register.sr3==1) /*v pp error */ error_handler ( ) ; if (status_register.sr1==1) /* locked block */ error_handler ( ) ; } while (status_register.sr7==1) x=0; /* initialize count */ do { writetoflash (start_address, dataflow[x]); x++; }while (x<32) do { status_register = readflash (start_address); }while (status_register.sr0==1) } while (not last data) writetoflash (another_block_address, ffffh) do { status_register = readflash (start_address) }while (status_register.sr7==0) full_status_register_check(); sr4 = 1 no no no no setup phase program and verify phase exit phase
77/83 m30l0r7000t0, m30l0r7000b0 appendix d. command interface state tables table 41. command interface states - modify table, next state current ci state command input read array (2) (ffh) program setup (3,4) (10/40h) buffer program (3,4) (e8h) block erase, setup (3,4) (20h) befp setup (80h) erase confirm p/e resume, block unlock confirm, befp confirm (3,4) (d0h) buffer program, program/ erase suspend (b0h) read status register (70h) clear status register (5) (50h) read electronic signature, read cfi query (90h, 98h) ready ready program setup buffer program setup erase setup befp setup ready lock/cr setup ready (lock error) ready (unlock block) ready (lock error) otp setup otp busy busy program setup program busy busy program busy program suspend program busy suspend program suspend program busy program suspend buffer program setup buffer program load 1 (give word count load (n-1)); buffer load 1 if n=0 go to buffer program confirm. else (n not =0) go to buffer program load 2 (data load) buffer load 2 buffer program confirm when count =0 ; else buffer program load 2 (note: buffer program will fail at this point if any block address is different from the first address) confirm ready (error) buffer program busy ready (error) busy buffer program busy buffer program suspend buffer program busy suspend buffer program suspend buffer program busy buffer program suspend erase setup ready (error) erase busy ready (error) busy erase busy erase suspend erase busy suspend erase suspend program in erase suspend buffer program setup in erase suspend erase suspend erase busy erase suspend program in erase suspend setup program busy in erase suspend busy program busy in erase suspend program suspend in erase suspend program busy in erase suspend suspend program suspend in erase suspend program busy in erase suspend program suspend in erase suspend
m30l0r7000t0, m30l0r7000b0 78/83 note: 1. ci = command interface, cr = configuration register, befp = buffer enhanced factory program, p/e. c. = program/erase con - troller. 2. at power-up, all banks are in read array mode. issuing a read array command to a busy bank, results in undetermined data out- put. 3. the two cycle command should be issued to the same bank address. 4. if the p/e.c. is active, both cycles are ignored. 5. the clear status register command clears the status register error bits except when the p/e.c. is busy or suspended. 6. befp is allowed only when status register bit sr0 is set to ?0?. befp is busy if block address is first befp address. any oth er commands are treated as data. buffer program in erase suspend setup buffer program load 1 in erase suspend (give word count load (n-1)); if n=0 go to buffer program confirm. else (n not =0) go to buffer program load 2 buffer load 1 buffer program load 2 in erase suspend (data load) buffer load 2 buffer program confirm in erase suspend when count =0 ; else buffer program load 2 in erase suspend (note: buffer program will fail at this point if any block address is different from the first address) confirm ready (error) buffer program busy in erase suspend ready (error) busy buffer program busy in erase suspend buffer program suspend in erase suspend buffer program busy in erase suspend suspend buffer program suspend in erase suspend buffer program busy in erase suspend buffer program suspend in erase suspend lock/cr setup in erase suspend erase suspend (lock error) erase suspend erase suspend (lock error) buffer efp setup ready (error) befp busy ready (error) busy befp busy (6) current ci state command input read array (2) (ffh) program setup (3,4) (10/40h) buffer program (3,4) (e8h) block erase, setup (3,4) (20h) befp setup (80h) erase confirm p/e resume, block unlock confirm, befp confirm (3,4) (d0h) buffer program, program/ erase suspend (b0h) read status register (70h) clear status register (5) (50h) read electronic signature, read cfi query (90h, 98h)
79/83 m30l0r7000t0, m30l0r7000b0 table 42. command interface states - modify table, next output state note: 1. the output state shows the type of data that appears at the outputs if the bank address is the same as the command addre ss. a bank can be placed in read array, read status register, read electronic signature or read cfi mode, depending on the com- mand issued. each bank remains in its last output state until a new command is issued to that bank. the next state does not dep end on the bank output state. 2. ci = command interface, cr = configuration register, befp = buffer enhanced factory program, p/e. c. = program/erase con- troller. 3. at power-up, all banks are in read array mode. issuing a read array command to a busy bank, results in undetermined data out- put. 4. the two cycle command should be issued to the same bank address. 5. if the p/e.c. is active, both cycles are ignored. current ci state command input read array (3) (ffh) program setup (4,5) (10/40h) buffer program (e8h) block erase, setup (4,5) (20h) befp setup (80h) erase confirm p/e resume, block unlock confirm, befp confirm (4,5) (d0h) program/ erase suspend (b0h) read status register (70h) clear status register (50h) read electronic signature, read cfi query (90h, 98h) program setup status register erase setup otp setup program in erase suspend befp setup befp busy buffer program setup buffer program load 1 buffer program load 2 buffer program confirm buffer program setup in erase suspend buffer program load 1 in erase suspend buffer program load 2 in erase suspend buffer program confirm in erase suspend lock/cr setup lock/cr setup in erase suspend otp busy array status register output unchanged status register output unchanged status register ready electronic signature/ cfi program busy erase busy buffer program busy program/erase suspend buffer program suspend program busy in erase suspend buffer program busy in erase suspend program suspend in erase suspend buffer program suspend in erase suspend
m30l0r7000t0, m30l0r7000b0 80/83 table 43. command interface states - lock table, next state note: 1. ci = command interface, cr = configuration register, befp = buffer enhanced factory program, p/e. c. = program/erase con - troller, wa0 = address in a block different from first befp address. 2. if the p/e.c. is active, both cycles are ignored. 3. befp exit when block address is different fr om first block address and data are ffffh. 4. befp is allowed only when status register bit sr0 is set to ?0?. befp is busy if block address is first befp address. any oth er commands are treated as data. 5. illegal commands are those not defined in the command set. 6. if n=0 go to buffer program confirm. else (n 0) go to buffer program load 2 (data load). 7. if n=0 go to buffer program confirm in erase suspend. else (n 0) go to buffer program load 2 in erase suspend. current ci state command input lock/cr setup (2) (60h) otp setup (2) (c0h) block lock confirm (01h) block lock-down confirm (2fh) set cr confirm (03h) block address (wa0) (3) (xxxxh) illegal command (5) wsm operation completed ready lock/cr setup otp setup ready n/a lock/cr setup ready (lock error) ready ready (lock error) n/a otp setup otp busy n/a busy ready program setup program busy n/a busy program busy ready suspend program suspend n/a buffer program setup buffer program load 1 (give word count load (n-1)); n/a buffer load 1 buffer program load 2 (6) exit see note (6) n/a buffer load 2 buffer program confirm when count =0; else buffer program load 2 (note: buffer program will fail at this point if any block address is different from the first address) n/a confirm ready (error) n/a busy buffer program busy ready suspend buffer program suspend n/a erase setup ready (error) n/a busy erase busy ready suspend lock/cr setup in erase suspend erase suspend n/a program in erase suspend setup program busy in erase suspend n/a busy program busy in erase suspend erase suspend suspend program suspend in erase suspend n/a buffer program in erase suspend setup buffer program load 1 in erase suspend (give word count load (n-1)) buffer load 1 buffer program load 2 in erase suspend (7) exit see note (7) buffer load 2 buffer program confirm in erase suspend when count =0; else buffer program load 2 in erase suspend (note: buffer program will fail at this point if any block address is different from the first address) confirm ready (error) busy buffer program busy in erase suspend suspend buffer program suspend in erase suspend lock/cr setup in erase suspend erase suspend (lock error) erase suspend erase suspend (lock error) n/a befp setup ready (error) n/a busy befp busy (4) exit befp busy (4) n/a
81/83 m30l0r7000t0, m30l0r7000b0 table 44. command interface states - lock table, next output state note: 1. the output state shows the type of data that appears at the outputs if the bank address is the same as the command addre ss. a bank can be placed in read array, read status register, read electronic signature or read cfi mode, depending on the com- mand issued. each bank remains in its last output state until a new command is issued to that bank. the next state does not dep end on the bank's output state. 2. ci = command interface, cr = configuration register, befp = buffer enhanced factory program, p/e. c. = program/erase con- troller, wa0 = address in a block different from first befp address. 3. if the p/e.c. is active, both cycles are ignored. 4. befp exit when block address is different fr om first block address and data are ffffh. 5. illegal commands are those not defined in the command set. current ci state command input lock/cr setup (3) (60h) otp setup (3) (c0h) block lock confirm (01h) block lock-down confirm (2fh) set cr confirm (03h) befp exit (4) (ffffh) illegal command (5) wsm operation completed program setup status register output unchanged erase setup otp setup program in erase suspend befp setup befp busy buffer program setup buffer program load 1 buffer program load 2 buffer program confirm buffer program setup in erase suspend buffer program load 1 in erase suspend buffer program load 2 in erase suspend buffer program confirm in erase suspend lock/cr setup status register array status register lock/cr setup in erase suspend otp busy status register output unchanged array output unchanged ready program busy erase busy buffer program busy program/erase suspend buffer program suspend program busy in erase suspend buffer program busy in erase suspend program suspend in erase suspend buffer program suspend in erase suspend
m30l0r7000t0, m30l0r7000b0 82/83 revision history table 45. document revision history date version revision details 05-may-2003 0.1 first issue 17-mar-2004 0.2 write to buffer and program command renamed buffer program command. clear status register command , set configuration register command and synchronous burst read mode clarified. table 15., program, erase times and endurance cycles reformatted, and buffer enhanced factory program timings added. in table 19., dc characteristics - currents , i dd1 , i dd2 , i dd3 , i dd4 , i dd6 and i dd7 , values changed and 16 word burst values added. v pp1 and v pplk values modified in table 20., dc characteristics - voltages . appendix a., block address tables reformatted. in appendix b., common flash interface , 0 added in front of 2-digit offset values. data modified at address offset (p + 1d)h = 127h in table 37., burst read information . figure 29., buffer enhanced factory program flowchart and pseudo code modified. appendix d., command interface state tables added. 03-dec-2004 1.0 figure 24., program suspend & resume flowchart and pseudo code , figure 25., block erase flowchart and pseudo code and figure 26., erase suspend & resume flowchart and pseudo code modified. flowchart modified and pseudo code added to figure 23., buffer program flowchart and pseudo code . small text changes. alt symbol for t avwh and t aveh removed from tables 23 and 24 , respectively. tfbga88 package fully compliant with the st ecopack specification. document status promoted from target specification to full datasheet.
83/83 m30l0r7000t0, m30l0r7000b0 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replac es all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. ecopack is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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